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1. (WO2010077778) STACKED DIE PARALLEL PLATE CAPACITOR
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/077778 International Application No.: PCT/US2009/067666
Publication Date: 08.07.2010 International Filing Date: 11.12.2009
IPC:
H01L 23/50 (2006.01) ,H01L 25/065 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
50
for integrated circuit devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
Applicants:
QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121, US (AllExceptUS)
CHANDRASEKARAN, Arvind [IN/US]; US (UsOnly)
Inventors:
CHANDRASEKARAN, Arvind; US
Agent:
TALPALATSKY, Sam; 5775 Morehouse Drive San Diego, California 92121, US
Priority Data:
12/336,78717.12.2008US
Title (EN) STACKED DIE PARALLEL PLATE CAPACITOR
(FR) CONDENSATEUR À PLAQUES PARALLÈLES À PUCES EMPILÉES
Abstract:
(EN) A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit includes a capacitor. The capacitor is formed by a first conducting plate on a region of the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode.
(FR) L'invention porte sur un circuit intégré empilé comprenant une première puce ayant une première surface et une seconde puce ayant une seconde surface faisant face à la première surface, le circuit intégré empilé comprenant un condensateur. Le condensateur est formé par une première plaque conductrice sur une région de la première surface, une seconde plaque conductrice sur une région de la seconde surface sensiblement alignée avec la première plaque conductrice, et un diélectrique entre la première électrode conductrice et la seconde électrode conductrice.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)