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1. WO2010077776 - SELF-TUNING OF SIGNAL PATH DELAY IN CIRCUIT EMPLOYING MULTIPLE VOLTAGE DOMAINS

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What is claimed is:

1. A circuit, comprising: a plurality of voltage domains; a plurality of paths; wherein each of the plurality of paths traverses a portion of the plurality of voltage domains and has a delay responsive to at least one of the plurality of voltage domains; and a delay circuit configured to generate a delay output related to the delay of the plurality of paths.

2. The circuit of claim 1, wherein the delay circuit is configured to produce the delay output according to a delay of a first path and a delay of a second path among the plurality of paths.

3. The circuit of claim 1, wherein the delay circuit is comprised of at least one gate configured to generate the delay output.

4. The circuit of claim 1, wherein the delay circuit is comprised of: one or more first delay elements whose voltages are supplied by a first voltage supply among the plurality of voltage domains and are configured to generate one or more first outputs; one or more second delay elements whose voltages are supplied by the second voltage supply among the plurality of voltage domains and configured to generate one or more second outputs; and at least one combining circuit configured to generate the delay output in response to receipt of the one or more first outputs and the one or more second outputs.

5. The circuit of claim 4, wherein the one or more first delay elements and one or more second delay elements are each comprised of one or more buffers.

6. The circuit of claim 1, further comprising at least one level shifter in one or more of the plurality of paths.

7. The circuit of claim 1, wherein the plurality of voltage domains comprises a lower voltage domain and a higher voltage domain.

8. The circuit of claim 7, wherein each of the plurality of paths traverses both the lower voltage domain and the higher voltage domain.

9. The circuit of claim 7, wherein a first path among the plurality of paths traverses the lower voltage domain, and a second path among the plurality of paths traverses the higher voltage domain.

10. The circuit of claim 1, wherein a first path among the plurality of paths is comprised of a sense path, and a second path among the plurality of paths is comprised of an access path coupled to at least one memory cell.

11. The circuit of claim 1 , wherein the circuit is used in an electronic device comprised from the group consisting of a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a digital music player, a portable music player, a digital video player, a digital video disc (DVD) player, and a portable digital video player.

12. A delay circuit, comprising: a plurality of voltage domains; a plurality of paths; wherein each of the plurality of paths traverses a portion of the plurality of voltage domains and has a delay responsive to at least one of the plurality of voltage domains; and a means for producing a delay output related to the delay of the plurality of paths.

13. A method of producing a delay output in a delay circuit, comprising: receiving a plurality of signals from a plurality of paths traversing a portion of a plurality of voltage domains, wherein the plurality of paths has a delay response to at least one of the plurality of voltage domains; delaying each of the plurality of signals related to the delay of a corresponding path of the plurality of paths; and generating a delay output from a delay circuit receiving the plurality of signals.

14. The method of claim 13, wherein delaying the plurality of signals further comprises delaying a received first signal among the plurality of signals in a first path among the plurality of paths according to a delay in a second path among the plurality of paths.

15. The method of claim 13, wherein generating the delay output comprises generating at least one gate output from the delay circuit receiving the plurality of signals.

16. The method of claim 13, wherein generating the delay output comprises: delaying a received first signal among the plurality of signals using one or more first delay elements whose voltages are supplied by a first voltage supply among the plurality of voltage domains; delaying the received first signal using one or more second delay elements whose voltages are supplied by a second voltage supply among the plurality of voltage domains; and combining the delayed first signal from the one or more first delay elements and the delayed first signal from the one or more second delay elements.

17. The method of claim 13, wherein receiving the plurality of signals comprises receiving the plurality of signals over both a lower voltage domain and a higher voltage domain among the plurality of voltage domains.

18. A memory system, comprising: a control system;

a plurality of voltage domains; a sense path traversing a first portion of the plurality of voltage domains and having a first delay responsive to the first portion; an access path traversing a second portion of the plurality of voltage domains having a second delay responsive to the second portion; and a delay circuit coupled to the sense path and configured to produce a delay output related to the first and second delays.

19. The memory system of claim 18, wherein the delay circuit is comprised of a plurality of delay elements each configured to generate the delay output.

20. The memory system of claim 18, wherein the delay circuit is comprised of: one or more first delay elements whose voltages are supplied by a first voltage supply among the plurality of voltage domains and are configured to generate one or more first outputs; one or more second delay elements whose voltages are supplied by the second voltage supply among the plurality of voltage domains and are configured to generate one or more second outputs; and at least one combining circuit configured to generate the delay output in response to receipt of the one or more first outputs and the one or more second outputs.

21. The memory system of claim 18 , wherein the plurality of voltage domains comprises a lower voltage domain and a higher voltage domain.

22. The memory system of claim 18, further comprising a plurality of sense amplifiers configured to receive the delay output.

23. The memory system of claim 22, wherein the plurality of sense amplifiers are configured to sense data from bit lines output from a memory cell array.

24. The memory system of claim 18, wherein the memory system is included in an electronic device comprised from the group consisting of a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a digital music player, a portable music player, a digital video player, a digital video disc (DVD) player, and a portable digital video player.