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1. (WO2010077776) SELF-TUNING OF SIGNAL PATH DELAY IN CIRCUIT EMPLOYING MULTIPLE VOLTAGE DOMAINS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/077776 International Application No.: PCT/US2009/067657
Publication Date: 08.07.2010 International Filing Date: 11.12.2009
IPC:
G11C 7/08 (2006.01) ,G11C 11/413 (2006.01) ,G11C 11/417 (2006.01) ,G11C 11/419 (2006.01) ,G11C 7/22 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
06
Sense amplifiers; Associated circuits
08
Control thereof
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
41
forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
41
forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
417
for memory cells of the field-effect type
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
41
forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
413
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
417
for memory cells of the field-effect type
419
Read-write (R-W) circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
22
Read-write (R-W) timing or clocking circuits; Read-write (R-W) control signal generators or management
Applicants:
QUALCOMM Incorporated [US/US]; Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121, US (AllExceptUS)
CHAI, Chiaming [US/US]; US (UsOnly)
LILES, Stephen Edward [US/US]; US (UsOnly)
Inventors:
CHAI, Chiaming; US
LILES, Stephen Edward; US
Agent:
TALPALATSKY, Sam; 5775 Morehouse Drive San Diego, California 92121, US
Priority Data:
12/336,74117.12.2008US
Title (EN) SELF-TUNING OF SIGNAL PATH DELAY IN CIRCUIT EMPLOYING MULTIPLE VOLTAGE DOMAINS
(FR) ACCORD AUTOMATIQUE DE RETARD DE CHEMIN DE SIGNAL DANS UN CIRCUIT UTILISANT DES DOMAINES DE TENSION MULTIPLES
Abstract:
(EN) Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.
(FR) L'invention porte sur des circuits et des procédés utilisés dans des domaines de tension multiples, qui comprennent un accord automatique ou une synchronisation d'un chemin de signal. Une pluralité de chemins sont formés dans le circuit. Chaque chemin traverse une partie des multiples domaines de tension, qui peut comprendre n'importe quel nombre ou n'importe quelle combinaison des multiples domaines de tension. Chacun des chemins présente un retard sensible à au moins l'un de la pluralité de domaines de tension. Un circuit à retard est utilisé et configuré pour générer une sortie de retard relative au retard dans la pluralité de chemins. De cette manière, la sortie de retard du circuit à retard est automatiquement réglée finement ou ajustée selon le retard dans la pluralité de chemins. Ce réglage fin automatique peut être particulièrement approprié pour régler le retard d'un premier chemin de signal par rapport à un second chemin de signal, les retards dans les chemins pouvant varier l'un par rapport à l'autre durant le fonctionnement.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP2380174JP2012512497CN102246236KR1020110106386BRPI0922986IN1110/MUMNP/2011