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1. (WO2010077467) METHOD OF FORMING GATE STACK AND STRUCTURE THEREOF
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/077467 International Application No.: PCT/US2009/065031
Publication Date: 08.07.2010 International Filing Date: 19.11.2009
IPC:
H01L 21/3205 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, NY 10504, US (AllExceptUS)
FREESCALE SEMICONDUCTOR INC. [US/US]; 6501 William Cannon Drive West Austin, TX 78735, US (AllExceptUS)
RAMACHANDRAN, Ravikumar [US/US]; US (UsOnly)
YAN, Hongwen [US/US]; US (UsOnly)
MOUMEN, Naim [DZ/US]; US (UsOnly)
SCHAEFFER, James, Kenyon [US/US]; US (UsOnly)
KRISHNAN, Siddarth, A. [IN/US]; US (UsOnly)
WONG, Keith, Kwong Hon [US/US]; US (UsOnly)
KWON, Unoh [KR/US]; US (UsOnly)
BELYANSKY, Michael, P. [RU/US]; US (UsOnly)
WISE, Richard [US/US]; US (UsOnly)
Inventors:
RAMACHANDRAN, Ravikumar; US
YAN, Hongwen; US
MOUMEN, Naim; US
SCHAEFFER, James, Kenyon; US
KRISHNAN, Siddarth, A.; US
WONG, Keith, Kwong Hon; US
KWON, Unoh; US
BELYANSKY, Michael, P.; US
WISE, Richard; US
Agent:
CAI, Yuanmin; International Business Machines Corporation Bldg. 321 - M/D 482 2070 Route 52 Hopewell Junction, NY 12533, US
Priority Data:
12/348,33205.01.2009US
Title (EN) METHOD OF FORMING GATE STACK AND STRUCTURE THEREOF
(FR) PROCÉDÉ DE FORMATION D'UN EMPILEMENT DE GÂCHETTE ET SA STRUCTURE
Abstract:
(EN) Embodiments of the present invention provide a method of forming gate stacks for field-effect- transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor substrate designated for first and second types of field-effect-transistors; forming a capping layer of a second TiN layer on top of the metal-containing layer; patterning the second TiN layer and the metal-containing layer to cover only a first portion of the first TiN layer, the first portion of the first TiN layer covering an area designated for the first type of field-effect-transistors; etching away a second portion of the first TiN layer exposed by the patterning while protecting the first portion of the first TiN layer, from the etching, through covering with at least a portion of thickness of the patterned metal-containing layer; and forming a third TiN layer covering an areas of the semiconductor substrate designated for the second type of field-effect-transistors.
(FR) Des modes de réalisation selon la présente invention concernent un procédé de formation d'empilements de gâchette pour des transistors à effet de champ. Le procédé consiste à former une couche contenant du métal directement sur une première couche de nitrure de titane (TiN), la première couche de TiN recouvrant des zones d'un substrat semi-conducteur conçu pour les premier et second types de transistors à effet de champ ; à former une couche de couverture d'une deuxième couche de TiN sur la couche contenant du métal ; à réaliser des motifs sur la deuxième couche de TiN et la couche contenant du métal pour ne recouvrir qu'une première partie de la première couche de TiN, la première couche de TiN recouvrant une zone désignée pour le premier type de transistors à effet de champ ; à graver une seconde partie de la première couche de TiN exposée par le traçage de motifs tout en protégeant la première partie de la première couche de TiN de la gravure, en recouvrant avec au moins une partie de l'épaisseur de la couche contenant du métal à motif ; et à former une troisième couche de TiN recouvrant une zone du substrat semi-conducteur désigné pour le second type de transistors à effet de champ.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP2377148JP2012514854CN102282655RU2011132473RU0002498446KR1020110102939