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1. (WO2010076926) MULTI-BIT FLASH MEMORY AND METHOD FOR MANUFACTURING THE SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/076926 International Application No.: PCT/KR2009/002388
Publication Date: 08.07.2010 International Filing Date: 07.05.2009
IPC:
H01L 27/115 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
Applicants:
한양대학교 산학협력단 INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY [KR/KR]; 서울 성동구 행당동 17번지 17 Haengdang-dong Seongdong-gu Seoul 133-791, KR (AllExceptUS)
김태환 KIM, Tae-Whan [KR/KR]; KR (UsOnly)
곽계달 KWACK, Kae-Dal [KR/KR]; KR (UsOnly)
김현주 KIM, Hyun-Joo [KR/KR]; KR (UsOnly)
Inventors:
김태환 KIM, Tae-Whan; KR
곽계달 KWACK, Kae-Dal; KR
김현주 KIM, Hyun-Joo; KR
Agent:
특허법인 이상 E-SANG PATENT & TRADEMARK LAW FIRM; 서울 서초구 양재동 82-2 우도빌딩 3층 3F. Woodo Bldg. 82-2 Yangjae-dong Seocho-gu Seoul 137-890, KR
Priority Data:
10-2008-013796431.12.2008KR
Title (EN) MULTI-BIT FLASH MEMORY AND METHOD FOR MANUFACTURING THE SAME
(FR) MÉMOIRE FLASH MULTI-BIT ET SON PROCÉDÉ DE FABRICATION
(KO) 멀티 비트 플래시 메모리 및 이를 제조하기 위한 방법
Abstract:
(EN) Disclosed is a flash memory having at least two gates prepared in one gate structure and a method for manufacturing the same. Each gate can store 1-bit data, and each cell transistor can store at least 2-bit information. In addition, the electric influence from adjacent floating gates is minimized while executing a program because of the varying thicknesses of each tunneling dielectric film. That is to say, electric charge trapping through a certain floating gate can be performed regardless of electromagnetic influence from the adjacent floating gates as a result of the height difference among the floating gates.
(FR) La présente invention concerne une mémoire flash comportant au moins deux grilles préparées dans une structure de grille et son procédé de fabrication. Chaque grille peut stocker des données à 1 bit, et chaque transistor de cellule peut stocker une information d'au moins 2 bits. En outre, l'influence électrique provenant des grilles flottantes adjacentes est minimisée lors de l'exécution d'un programme en raison des épaisseurs variables de chaque film diélectrique de transmission tunnel. En d'autres mots, le piègeage de la charge électrique à travers une grille flottante peut être effectuée indépendamment de l'influence électromagnétique provenant des grilles flottantes adjacentes grâce à la différence de hauteur entre les grilles flottantes adjacentes.
(KO) 하나의 게이트 구조물에 구비된 적어도 2개의 게이트를 가진 플래시 메모리 및 이를 제조하는 방법이 개시된다. 각각의 게이트는 1비트의 데이터를 저장할 수 있으며, 하나의 셀 트랜지스터는 적어도 2비트의 정보를 저장할 수 있다. 또한, 각각의 터널링 유전막의 두께는 달리 설정되어, 프로그램 동작 시에 인접한 부유 게이트에 의한 전기적 영향은 최소화된다. 즉, 서로 다른 높이를 가지는 부유 게이트에 의해 특정의 부유 게이트를 통한 전하의 트랩동작은 인접한 부유 게이트에 의한 전자기적 영향을 배제한 채 수행할 수 있다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)