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1. (WO2010076825) DOUBLE PATTERNING METHOD FOR CREATING A REGULAR ARRAY OF PILLARS WITH DUAL SHALLOW TRENCH ISOLATION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/076825 International Application No.: PCT/IT2008/000813
Publication Date: 08.07.2010 International Filing Date: 30.12.2008
IPC:
H01L 27/102 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
102
including bipolar components
Applicants:
NUMONYX B.V. [CH/CH]; Zone d'activités La Pièce 2 A-One Business Center, Route de l'Etraz CH-1180 Rolle, CH (AllExceptUS)
PELLIZER, Fabio [IT/IT]; IT (UsOnly)
MARIANI, Marcello [IT/IT]; IT (UsOnly)
SERVALLI, Giorgio [IT/IT]; IT (UsOnly)
Inventors:
PELLIZER, Fabio; IT
MARIANI, Marcello; IT
SERVALLI, Giorgio; IT
Agent:
FAGGIONI, Carlo Maria; Fumero Studio Consulenza Brevetti Via S. Agnese 12 I-20123 MILANO, IT
Priority Data:
Title (EN) DOUBLE PATTERNING METHOD FOR CREATING A REGULAR ARRAY OF PILLARS WITH DUAL SHALLOW TRENCH ISOLATION
(FR) PROCÉDÉ POUR DOUBLE MOTIF POUR CRÉER UNE MATRICE RÉGULIÈRE DE PILIERS À DOUBLE ISOLATION DE TRANCHÉE PEU PROFONDE
Abstract:
(EN) A method is disclosed for forming vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a width below the minimum lithographical resolution F of the lithographic technique employed. In an embodiment, the pillar array features have a dimension of approximately F/2, though this dimension could be reduced down to other values compatible with embodiments of the invention. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.
(FR) L'invention concerne un procédé de formation de transistors à jonction bipolaire verticale comprenant une matrice régulière de piliers de contact de base et de piliers de contact émetteurs dont la largeur est inférieure à la résolution lithographique minimale F de la technique lithographique employée. Dans un mode de réalisation, les caractéristiques de la matrice de piliers présentent une dimension d'environ F/2, bien que cette dimension puisse être réduite à d'autres valeurs compatibles avec des modes de réalisation selon l'invention. Un élément d'enregistrement, comme un élément d'enregistrement à changement de phase, peut être formé au-dessus de la matrice régulière de piliers de contact de base et de piliers de contact émetteurs.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20110248382