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1. (WO2010076649) PACKET PROCESSING SYSTEM ON CHIP DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/076649 International Application No.: PCT/IB2009/007914
Publication Date: 08.07.2010 International Filing Date: 31.12.2009
IPC:
H04L 12/46 (2006.01) ,G06F 15/78 (2006.01) ,G06F 17/50 (2006.01) ,G06F 21/00 (2006.01) ,H04L 12/42 (2006.01) ,H04L 12/56 (2006.01)
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12
Data switching networks
28
characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
46
Interconnection of networks
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
76
Architectures of general purpose stored programme computers
78
comprising a single central processing unit
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
50
Computer-aided design
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
21
Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12
Data switching networks
28
characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
42
Loop networks
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12
Data switching networks
54
Store-and-forward switching systems
56
Packet switching systems
Applicants:
TRANSWITCH INDIA PVT. LTD. [IN/IN]; A-27 Mohan Co-operative Industrial Estate Mathura road 110044 New Delhi, IN (AllExceptUS)
MALIK, Rakesh, Kumar [IN/IN]; IN (UsOnly)
BERT, Klaps [BE/BE]; BE (UsOnly)
HANSPAL, Jagmeet, Singh [IN/IN]; IN (UsOnly)
KUNAL, Prasad [IN/IN]; IN (UsOnly)
GUJRAL, Amandeep, Singh [IN/IN]; IN (UsOnly)
SHANLEY, Timothy, M. [US/US]; US (UsOnly)
SURI, Kapil [IN/IN]; IN (UsOnly)
GUPTA, Dinesh [IN/IN]; IN (UsOnly)
BARMAN, Arun, Kumar [IN/IN]; IN (UsOnly)
ANAND, Prashant [IN/IN]; IN (UsOnly)
PUROHIT, Milan, Vinodrai [IN/IN]; IN (UsOnly)
GUPTA, Neeraj [IN/IN]; IN (UsOnly)
BANERJEE, Pradeept, Kumar [IN/IN]; IN (UsOnly)
DIXIT, Priyadarshini [IN/IN]; IN (UsOnly)
Inventors:
MALIK, Rakesh, Kumar; IN
BERT, Klaps; BE
HANSPAL, Jagmeet, Singh; IN
KUNAL, Prasad; IN
GUJRAL, Amandeep, Singh; IN
SHANLEY, Timothy, M.; US
SURI, Kapil; IN
GUPTA, Dinesh; IN
BARMAN, Arun, Kumar; IN
ANAND, Prashant; IN
PUROHIT, Milan, Vinodrai; IN
GUPTA, Neeraj; IN
BANERJEE, Pradeept, Kumar; IN
DIXIT, Priyadarshini; IN
Agent:
GOPALAN, Deepak, Sriniwas; K & S Partners B.K. House, Plot No. 109 Sector-44 Gurgaon 122 002 Haryana, IN
Priority Data:
2742/MUM/200831.12.2008IN
2744/MUM/200831.12.2008IN
2745/MUM/200831.12.2008IN
2746/MUM/200831.12.2008IN
Title (EN) PACKET PROCESSING SYSTEM ON CHIP DEVICE
(FR) SYSTÈME DE TRAITEMENT PAR PAQUETS SUR UN DISPOSITIF À PUCE
Abstract:
(EN) The present invention relates to the area of packet processing system on chip device which that estimates the queue fill level for a particular type of data stored in the data storage device, enables sharing of the data storage unit between different units that have different traffic characteristics as per their traffic requirements and ensure that traffic from any one does not adversely impact the other, enhances the performance of the memory by modifying the memory access pattern and maintains a certain rate of reading the packet fragments from the DDR at the transmission end.
(FR) La présente invention concerne un système de traitement par paquets sur un dispositif à puce permettant d'estimer le niveau de remplissage de la file d'attente pour un type particulier de données stockées dans le dispositif de stockage, permettant le partage d'une unité de stockage de données entre différentes unités possédant différentes caractéristiques de trafic conformément aux exigences desdites unités en matière de trafic et garantissant que le trafic provenant d'une des unités ne nuit pas à une autre unité, permettant d'optimiser la performance de la mémoire en modifiant le motif d'accès mémoire et de maintenir une certaine vitesse de lecture des fragments de paquets provenant du DDR à l'extrémité de transmission.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)