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1. (WO2010076074) INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/076074 International Application No.: PCT/EP2009/064974
Publication Date: 08.07.2010 International Filing Date: 11.11.2009
IPC:
H01L 21/768 (2006.01) ,H01L 23/532 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532
characterised by the materials
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, New York 10504, US (AllExceptUS)
IBM UNITED KINGDOM LIMITED [GB/GB]; PO Box 41, North Harbour Portsmouth Hampshire PO6 3AU, GB (MG)
BASKER, Veeraraghavan [IN/US]; US (UsOnly)
TONTI, William, Robert [US/US]; US (UsOnly)
WONG, Keith, Kwong Hon [US/US]; US (UsOnly)
YANG, Chih-Chao [US/US]; US (UsOnly)
Inventors:
BASKER, Veeraraghavan; US
TONTI, William, Robert; US
WONG, Keith, Kwong Hon; US
YANG, Chih-Chao; US
Agent:
ROBERTS, Scott; IBM United Kingdom Limited Intellectual Property Law Hursley Park Winchester Hampshire SO21 2JN, GB
Priority Data:
12/346,04030.12.2008US
Title (EN) INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME
(FR) STRUCTURE D'INTERCONNEXION À LIGNE DIÉLECTRIQUE AMÉLIORÉE À UNE COUCHE INTERFACIALE RÉSISTANT À L'ÉLECTROMIGRATION DE TROU D'INTERCONNEXION ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) (66) that is present at the bottom of a via opening. The via opening is located within a second dielectric material (52') that is located atop a first dielectric material (52) that includes a first conductive material (56) embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
(FR) L'invention porte sur des structures d'interconnexion possédant une résistance à l'électromigration améliorée qui comprennent une couche interfaciale métallique (ou couche d'alliage métallique) (66) qui est présente au fond d'une ouverture de trou d'interconnexion. L'ouverture de trou d'interconnexion est située dans un second matériau diélectrique (52') qui se trouve au-dessus d'un premier matériau diélectrique (52) qui comprend un premier matériau conducteur (56) incorporé dans celui-ci. La couche interfaciale métallique (ou couche d'alliage métallique) qui est présente au fond de l'ouverture de trou d'interconnexion est située entre le premier matériau conducteur sous-jacent incorporé dans le premier matériau diélectrique et le second matériau conducteur qui est incorporé dans le second matériau diélectrique. L'invention porte également sur des procédés de fabrication des structures d'interconnexion à résistance à l'électromigration améliorée.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP2356677JP2012514321CN102246293