Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2010076056) STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/076056 International Application No.: PCT/EP2009/064260
Publication Date: 08.07.2010 International Filing Date: 29.10.2009
IPC:
H01L 21/60 (2006.01) ,H01L 23/485 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482
consisting of lead-in layers inseparably applied to the semiconductor body
485
consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, New York 10504, US (AllExceptUS)
GAMBINO, Jeffrey [US/US]; US (UsOnly)
DAUBENSPECK, Timothy, Harrison [US/US]; US (UsOnly)
MUZZY, Christopher, David [US/US]; US (UsOnly)
SAUTER, Wolfgang [DE/US]; US (UsOnly)
SULLIVAN, Timothy, Dooling [US/US]; US (UsOnly)
Inventors:
GAMBINO, Jeffrey; US
DAUBENSPECK, Timothy, Harrison; US
MUZZY, Christopher, David; US
SAUTER, Wolfgang; US
SULLIVAN, Timothy, Dooling; US
Agent:
WILLIAMS, Julian, David; IBM United Kingdom Limited Intellectual Property Law Hursley Park Winchester Hampshire SO21 2JN, GB
Priority Data:
12/344,80229.12.2008US
Title (EN) STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES
(FR) STRUCTURES ET PROCÉDÉS D'AMÉLIORATION DES CONNEXIONS PAR PERLE DE SOUDURE DANS DES DISPOSITIFS À SEMI-CONDUCTEURS
Abstract:
(EN) Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming a plurality of trenches in a dielectric layer extending to an underlying metal layer. The method further includes depositing metal in the plurality of trenches to form discrete metal line islands in contact with the underlying metal layer. The method also includes forming a solder bump in electrical connection to the plurality of metal line islands.
(FR) L'invention porte sur des structures à connexions par perle de soudure améliorées et sur des procédés de fabrication de ces structures. Le procédé comprend la formation d'une pluralité de tranchées dans une couche diélectrique s'étendant jusqu'à une couche métallique sous-jacente. Le procédé comprend en outre le dépôt de métal dans la pluralité de tranchées afin de former des îlots de ligne métallique discrets en contact avec la couche métallique sous-jacente. Le procédé comprend également la formation d'une perle de soudure en connexion électrique avec la pluralité d'îlots de ligne métallique.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
JP2012514320