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1. (WO2010076018) REDUCTION OF THRESHOLD VOLTAGE VARIATION IN TRANSISTORS COMPRISING A CHANNEL SEMICONDUCTOR ALLOY BY REDUCING DEPOSITION NON-UNIFORMITIES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/076018 International Application No.: PCT/EP2009/009307
Publication Date: 08.07.2010 International Filing Date: 29.12.2009
IPC:
H01L 21/8234 (2006.01) ,H01L 21/8238 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
Applicants:
ADVANCED MICRO DEVICES, INC [US/US]; One AMD Place, Mail Stop 68 Sunnyvale, CA 94088-3453, US (AllExceptUS)
AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG [DE/DE]; Wilschdorfer Landstrasse 101 01109 Dresden, DE (AllExceptUS)
KRONHOLZ, Stephan [DE/DE]; DE (UsOnly)
OTT, Andreas [DE/DE]; DE (UsOnly)
Inventors:
KRONHOLZ, Stephan; DE
OTT, Andreas; DE
Agent:
PFAU, Anton, K.; Grünecker Kinkeldey, Stockmair & Schwanhäusser Leopoldstrasse 4 80802 München, DE
Priority Data:
10 2008 063 402.631.12.2008DE
12/637,11214.12.2009US
Title (EN) REDUCTION OF THRESHOLD VOLTAGE VARIATION IN TRANSISTORS COMPRISING A CHANNEL SEMICONDUCTOR ALLOY BY REDUCING DEPOSITION NON-UNIFORMITIES
(FR) RÉDUCTION DE LA VARIATION DE LA TENSION DE SEUIL DANS LES TRANSISTORS COMPRENANT UN ALLIAGE SEMI-CONDUCTEUR DE CANAL EN RÉDUISANT LES NON-UNIFORMITÉS DE DÉPÔT
Abstract:
(EN) A threshold adjusting semiconductor material, such as a silicon/germanium alloy may be provided selectively for one type of transistors on the basis of enhanced deposition uniformity. For this purpose, the semiconductor alloy may be deposited on the active regions of any transistors and may subsequently be patterned on the basis of a highly controllable patterning regime. Consequently, threshold variability may be reduced.
(FR) Le matériau semi-conducteur d'ajustement de seuil selon l'invention, comme un alliage silicium/germanium peut être réalisé sélectivement pour un type de transistors sur la base de l'uniformité de dépôt améliorée. Dans ce but, l'alliage semi-conducteur peut être déposé sur les zones actives de n'importe quel transistor et peut par conséquent recevoir un motif sur la base d'un régime de traçage de motif fortement contrôlé. Cela permet par conséquent de réduire la variabilité du seuil.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
JP2012514318CN102341906KR1020120067973IN4995/DELNP/2011