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1. (WO2010076017) A TRANSISTOR WITH AN EMBEDDED STRAIN INDUCING MATERIAL HAVING A GRADUALLY SHAPED CONFIGURATION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/076017 International Application No.: PCT/EP2009/009306
Publication Date: 08.07.2010 International Filing Date: 29.12.2009
IPC:
H01L 21/8234 (2006.01) ,H01L 21/8238 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
ADVANCED MICRO DEVICES, INC [US/US]; One AMD Place Mail Stop 68 Sunnyvale, CA 94088-3453, US (AllExceptUS)
AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG [DE/DE]; Wilschdorfer Landstrasse 101 01109 Dresden, DE (AllExceptUS)
KRONHOLZ, Stephan [DE/DE]; DE (UsOnly)
PAPAGEORGIOU, Vassilios [DE/DE]; DE (UsOnly)
BEERNINK, Gunda [DE/DE]; DE (UsOnly)
Inventors:
KRONHOLZ, Stephan; DE
PAPAGEORGIOU, Vassilios; DE
BEERNINK, Gunda; DE
Agent:
PFAU, Anton, K.; Grünecker, Kinkeldey, Stockmair & Schwanhäusser Leopoldstrasse 4 80802 München, DE
Priority Data:
10 2008 063 427.131.12.2008DE
12/640,76517.12.2009US
Title (EN) A TRANSISTOR WITH AN EMBEDDED STRAIN INDUCING MATERIAL HAVING A GRADUALLY SHAPED CONFIGURATION
(FR) TRANSISTOR AVEC MATÉRIAU INDUISANT LA CONTRAINTE INCORPORÉ PRÉSENTANT UNE CONFIGURATION FORMÉE GRADUELLEMENT
Abstract:
(EN) In a transistor a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain- inducing semiconductor alloy. For this purpose, two or more "disposable" spacer elements of different etch behaviour may be used in order to define different lateral off-sets at different depths of the corresponding cavities. Consequently, enhanced uniformity and thus reduced transistor variability may be accomplished even for sophisticated semiconductor devices.
(FR) Dans le transistor selon l'invention un alliage semi-conducteur induisant une contrainte, comme les alliages silicium/germanium, silicium/carbone et similaires peut être positionné très près de la zone de canal en présentant des cavités formées graduellement qui peuvent alors être remplies de l'alliage semi-conducteur induisant une contrainte. Dans ce but, deux éléments d'entretoise « amovibles » ou plus de comportement de gravure différent peuvent être utilisés afin de définir différents décalages latéraux à différentes profondeurs des cavités correspondantes. Cela permet de réaliser une uniformité améliorée et donc de réduire la variabilité d'un transistor même dans les dispositifs semi-conducteurs sophistiqués.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
JP2012514317CN102362344KR1020120030033IN4994/DELNP/2011