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1. (WO2010075815) METHOD, APPARATUS AND SYSTEM FOR TESTING INTEGRATED CIRCUITS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/075815 International Application No.: PCT/CN2010/000071
Publication Date: 08.07.2010 International Filing Date: 15.01.2010
IPC:
H01L 21/66 (2006.01) ,G01R 31/26 (2006.01) ,G01R 31/28 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
66
Testing or measuring during manufacture or treatment
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
26
Testing of individual semiconductor devices
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
Applicants:
上海芯豪微电子有限公司 SHANGHAI XINHAO MICRO-ELECTRONICS CO. LTD. [CN/CN]; 中国上海市四平路1398号B座1202室林正浩 c/o LIN, Kenneth, Cheng Hao Suite 1202, Building B 1398 Siping Road Shanghai 200092, CN (AllExceptUS)
林正浩 LIN, Kenneth, Cheng Hao [US/CN]; CN (UsOnly)
Inventors:
林正浩 LIN, Kenneth, Cheng Hao; CN
Priority Data:
200910044937.803.01.2009CN
Title (EN) METHOD, APPARATUS AND SYSTEM FOR TESTING INTEGRATED CIRCUITS
(FR) PROCÉDÉ, APPAREIL ET SYSTÈME POUR TESTER DES CIRCUITS INTÉGRÉS
(ZH) 集成电路并行测试方法、装置和系统
Abstract:
(EN) A method, apparatus and system for testing integrated circuits are disclosed. A plurality of devices under test and a plurality of operation result comparison devices are in a common substrate. Identical input stimulations are applied to each of the plurality of devices under test and operation results are generated. The operation results are compared by using the corresponding comparison devices and compared features are obtained. Failure devices under test are sorted out according to the compared features.
(FR) La présente invention concerne un procédé, un appareil et un système pour tester des circuits intégrés. Une pluralité de dispositifs à l'essai et une pluralité de dispositifs de comparaison des résultats d'opération sont placés sur un substrat commun. Des stimulations d'entrée identiques sont appliquées à chacun des multiples dispositifs à l'essai et des résultats d'opération sont générés. Les résultats d'opération sont comparés au moyen des dispositifs de comparaison correspondants puis les caractéristiques comparées sont obtenues. Les dispositifs défaillants à l'essai sont triés en fonction des caractéristiques comparées.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)