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1. (WO2010075684) MEMORY
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/075684 International Application No.: PCT/CN2009/071775
Publication Date: 08.07.2010 International Filing Date: 13.05.2009
IPC:
H01L 21/8238 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
Applicants:
上海宏力半导体制造有限公司 GRACE SEMICONDUCTOR MANUFACTURING CORP. [CN/CN]; 中国上海市 浦东新区张江高科技园区郭守敬路818号 818 Guoshoujing Road, Zhangjiang Hi-Tech Park, Pudong Shanghai 201203, CN (AllExceptUS)
孔蔚然 KONG, Weiran [CN/CN]; CN (UsOnly)
Inventors:
孔蔚然 KONG, Weiran; CN
Agent:
上海光华专利事务所 J. Z. M. C PATENT AND TRADEMARK LAW OFFICE; 中国上海市 杨浦区国定路335号5022室余明伟 YU, Mingwei Room 5022 No.335, Guoding Road Yang Pu Shanghai 200433, CN
Priority Data:
200910044889.205.01.2009CN
Title (EN) MEMORY
(FR) MÉMOIRE
(ZH) 存储器
Abstract:
(EN) A memory includes: a semiconductor substrate (1), a doped source area (2) and a doped drain area (3) set in the semiconductor substrate (1), and a channel area (4) set between said doped source area (2) and said doped drain area (3); a first insulating layer (5) located on the semiconductor substrate (1), a charge memory layer (6) composed of polysilicon located on said first insulating layer (5); a SiGe conducting layer (7) set in said charge memory layer (6).
(FR) L'invention porte sur une mémoire qui comprend : un substrat semi-conducteur (1), une zone de source dopée (2) et une zone de drain dopée (3) formées dans le substrat semi-conducteur (1) et une zone de canal (4) formée entre ladite zone de source dopée (2) et ladite zone de drain dopée (3) ; une première couche isolante (5) placée sur le substrat semi-conducteur (1), une couche de mémoire de charge (6) composée de polysilicium placée sur ladite première couche isolante (5) ; une couche conductrice SiGe (7) formée dans ladite couche de mémoire de charge (6).
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)
Also published as:
US20110037119