Search International and National Patent Collections
Some content of this application is unavailable at the moment.
If this situation persists, please contact us atFeedback&Contact
1. (WO2010074973) TRIGATE STATIC RANDOM-ACCESS MEMORY WITH INDEPENENT SOURCE AND DRAIN ENGINEERING, AND DEVICES MADE THEREFROM
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/074973 International Application No.: PCT/US2009/067281
Publication Date: 01.07.2010 International Filing Date: 09.12.2009
IPC:
H01L 21/8244 (2006.01) ,H01L 27/11 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8244
Static random access memory structures (SRAM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
11
Static random access memory structures
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95052, US (AllExceptUS)
PILLARESITTY, Ravi [US/US]; US (UsOnly)
RACHMADY, Willy [ID/US]; US (UsOnly)
DOYLE, Brian [US/US]; US (UsOnly)
CHAU, Robert S. [US/US]; US (UsOnly)
Inventors:
PILLARESITTY, Ravi; US
RACHMADY, Willy; US
DOYLE, Brian; US
CHAU, Robert S.; US
Agent:
VINCENT, Lester J.; Blakely Sokoloff Taylor & Zafman 1279 Oakmead Parkway Sunnyvale, California 94085, US
Priority Data:
12/317,53624.12.2008US
Title (EN) TRIGATE STATIC RANDOM-ACCESS MEMORY WITH INDEPENENT SOURCE AND DRAIN ENGINEERING, AND DEVICES MADE THEREFROM
(FR) MÉMOIRE VIVE STATIQUE TRIPLE PORTE AVEC UNE TECHNOLOGIE DE SOURCE ET DRAIN INDÉPENDANTS, ET PÉRIPHÉRIQUES FABRIQUÉS À PARTIR DE CELLE-CI
Abstract:
(EN) A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for the pull-down region to be lower than Rext for the pass region. Processes of achieving the static random-access memory circuit include source-and-drain epitaxy.
(FR) La présente invention concerne un circuit de mémoire vive statique comprenant au moins un périphérique d'accès comportant des sections source et drain pour une région de transition, au moins un dispositif de tirage et au moins un dispositif de polarisation vers la masse comprenant des sections de source et de drain pour une région de polarisation vers la masse. Le circuit de mémoire vive statique est conçu de telle sorte que la résistivité externe (Rext) de la région de polarisation vers la masse est inférieure à la Rext de la région de transition. Les procédés permettant de réaliser le circuit de mémoire vive statique comprennent l'épitaxie de la source et du drain.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP2368267JP2012509601CN102171813KR1020110050721EP3208849