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1. (WO2010074939) SYSTEM AND METHOD FOR ISOLATED NMOS-BASED ESD CLAMP CELL
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WE CLAIM:

1. An ESD protection circuit for an integrated circuit chip, comprising: an isolated NMOS transistor comprising: an isolation region isolating a backgate from a substrate, and a first and second doped regions and a gate formed on the backgate; a first terminal to connect the isolation region to a first electrical node; and a second terminal to connect the second doped region to a second electrical node, wherein the first electrical node has a higher voltage level than the second electrical node, and the gate and backgate are coupled to the second terminal.

2. The ESD protection circuit of claim 1, wherein the first doped region is a drain and the second doped region is a source of the isolated NMOS transistor.

3. The ESD protection circuit of claim 2, wherein the isolated MOS transistor is off during operation of the integrated circuit chip.

4. The ESD protection circuit of claim 2, wherein the drain is not connected to any terminal and is floating.

5. The ESD protection circuit of claim 2, wherein the drain is connected to the first terminal and the isolation region.

6. The ESD protection circuit of claim 2, wherein the drain is connected to the second terminal and the source.

7. The ESD protection circuit of claim 2, wherein the backgate is to be coupled to the second terminal via a backgate doped region.

8. The ESD protection circuit of claim 2, wherein the backgate is to be coupled to the second terminal via a resistor.

9. The ESD protection circuit of claim 8, wherein the resistor has an adjustable resistance.

10. The ESD protection circuit of claim 1, wherein the first electrical node is a first power supply of a high voltage level and the second electrical node is a second power supply of a lower voltage level.

11. An ESD protection circuit for an integrated circuit chip, comprising: an isolated MOS transistor comprising: an isolation region isolating a backgate from a substrate, and a first and second doped regions and a gate formed on the backgate; a first terminal to connect the isolation region to a first electrical node; a second terminal to connect the backgate to a second electrical node; and a third terminal to connect the first doped region to a third electrical node, wherein the first electrical node has a higher voltage level than the third electrical node and the third electrical node has a higher voltage level than the second electrical node.

12. The ESD protection circuit of claim 11, wherein the first doped region is a source and the second doped region is a drain of the isolated NMOS transistor.

13. The ESD protection circuit of claim 12, wherein the isolated MOS transistor is off during operation of the integrated circuit chip.

14. The ESD protection circuit of claim 12, wherein the drain is not connected to any terminal and is floating.

15. The ESD protection circuit of claim 12, wherein the drain is connected to the source and is connected to the third power supply.

16. The ESD protection circuit of claim 12, wherein the gate is connected to the source.

17. The ESD protection circuit of claim 11, wherein the first doped region is a drain and the second doped region is a source of the isolated NMOS transistor.

18. The ESD protection circuit of claim 17, wherein the backgate is to be coupled to the second terminal via a backgate doped region.

19. The ESD protection circuit of claim 17,wherein the backgate is to be coupled to the second terminal via a resistor.

20. The ESD protection circuit of claim 17,wherein the resistor has an adjustable resistance.

21. The ESD protection circuit of claim 17, wherein the gate is connected to the source.

22. The ESD protection circuit of claim 17, wherein each of the electrical nodes is connected to a power supply.

23. An integrated circuit chip, comprising: a plastic casing with a plurality of pins; an integrated circuit die connected to the pins, the integrated circuit die including an isolated NMOS transistor comprising: an isolation region isolating a backgate from a substrate, and a first and second doped regions and a gate formed on the backgate; a first terminal to connect the isolation region to a first electrical node; and a second terminal to connect the second doped region to a second electrical node, wherein the first electrical node has a higher voltage level than the second electrical node, and the gate and backgate are coupled to the second terminal via a first resistor and second resistor, the second resistor has an adjustable resistance, the gate is connected to a source of the NMOS transistor.

24. An integrated circuit chip, comprising: a plastic casing with a plurality of pins; an integrated circuit die connected to the pins, the integrated circuit die including an isolated NMOS transistor comprising: an isolation region isolating a backgate from a substrate, and a first and second doped regions and a gate formed on the backgate; a first terminal to connect the isolation region to a first electrical node; a second terminal to connect the backgate to a second electrical node; and a third terminal to connect the first doped region to a third electrical node, wherein the first electrical node has a higher voltage level than the third electrical node and the third electrical node has a higher voltage level than the second electrical node, the backgate is to be coupled to the second terminal via a resistor with an adjustable resistance, the gate is connected to a source of the NMOS transistor.