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1. (WO2010074904) RANDOM ACCESS MEMORY ARCHITECTURE INCLUDING MIDPOINT REFERENCE
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CLAIMS

1. A random access memory architecture comprising: an array of memory cells, each memory cell having a programmable state comprising one of a first resistance state and a second resistance state; and a midpoint reference coupled between a first node and a second node and having a resistance between that of the first resistance state and the resistance of the second resistance state, comprising: a first memory element coupled to the first node and having a programmable state comprising one of the first resistance state and the second resistance state; a second memory element coupled to the second node and having a programmable state comprising one of the first resistance state and the second resistance state coupled to the first memory cell: and circuitry selectively coupled to either the first or second memory element in order to sense whether the coupled first or second memory element is in the first or second resistance state.

2. The random access memory of claim 1 further comprising: a third memory element coupled to the first node and having a programmable state comprising one of the first resistance state and the second resistance state; and a fourth memory element coupled to the second node and having a programmable state comprising one of the first resistance state and the second resistance state coupled to the third memory element; wherein the circuitry is further selectively coupled to either the third or fourth memory element in order to sense whether the coupled third or fourth memory element is in the first or second resistance state.

3. The random access memory of claim 2 wherein the third memory element is further coupled to the second memory element.

4. The random access memory architecture of claim 1 wherein the first memory element comprises a first series connected pair of memory elements and the second memory element comprises a second series connected pair of memory elements, the random access memory architecture further comprising: a sense amplifier coupled to the array of memory cells; and a voltage bias portion coupled to the sense amplifier, the voltage bias portion including the first and second memory elements.

5. The random access memory architecture of claim 1 further comprising: the array of memory cells comprising at least one data column of memory cells coupled to have information stored within at least one memory cell, each memory cell including at least one non- volatile memory element programmable to one of the first state of resistance and the second state of resistance; a circuit positioned adjacent the at least one data column, having a net resistance between the first data state and second state states of resistance; and a differential read-out circuit coupled to the at least one data column for differentially comparing a data current generated from the non-symmetric memory element to a reference current generated from the circuit and providing a data output signal, wherein the differential read-out circuit includes the first and second memory elements.

6. The random access memory architecture of claim 4 wherein the voltage bias circuit comprises: a first transistor of a first conductivity type having a first current electrode coupled to a first node, a second current electrode coupled to a second node, and a control electrode coupled to a reference voltage; a second transistor of a second conductivity type having a first current electrode coupled to the second node; a second current electrode coupled to a drain voltage, and a control electrode coupled to the second node; a third transistor of a first conductivity type having a first current electrode coupled to the first node, a second current electrode coupled to the second node, and a control electrode coupled to the reference voltage; and a fourth transistor of the second conductivity type having a first current electrode coupled to the second node, a second current electrode coupled to a drain voltage, and a control electrode coupled to the second node; wherein the first and second memory elements are coupled between the first node and a voltage source.

7. A random access memory architecture comprising: a plurality of non-symmetric memory elements, each capable of having a first state of resistance and a second state of resistance, wherein the resistance when the current is flowing therethrough in a first direction is not equal to the resistance when the current is flowing therethrough in a second direction; a first series connected pair of memory elements having a first resistance and a second resistance, respectively, and disposed wherein a current flows in the first direction through both of the first series connected pair of memory elements; and a second series connected pair of memory elements having a third and a fourth resistance, respectively, coupled in parallel with the first series connected pair of memory elements, and disposed wherein a current flows in the first direction through both of the second series connected pair of memory elements.

8. The random access memory architecture of claim 7 wherein the first series connected pair of memory elements comprises first and second memory elements and the second series connected pair of memory elements comprises third and fourth memory elements, the random access memory architecture further comprising: a first voltage reference coupled to a first side of the first and third memory elements; a first transistor coupled between a second side of the first memory element and a first node; a second transistor coupled between a second side of the third memory element and the first node, the first node being coupled to a first side of both the second and fourth memory elements; a third transistor coupled between a second side of the second memory element and a first read bit line; and a fourth transistor coupled between a second side of the fourth memory element and the first read bit line.

9. The random access memory architecture of claim 8 further comprising: a fifth transistor coupled between the second side of the first memory element and the first read bit line; a sixth transistor coupled between the second side of the third memory element and a second read bit line; and a seventh transistor coupled between the first node and the first voltage reference.

10. The random access memory architecture of claim 7 wherein the first series connected pair of memory elements comprises first and second memory elements and the second series connected pair of memory elements comprises third and fourth memory elements, the random access memory architecture further comprising: a sense amplifier coupled to the plurality of non- symmetric memory elements; and a voltage bias portion coupled to the sense amplifier, the voltage bias portion including the first and second series connected pair of memory elements.

11. The random access memory architecture of claim 7 further comprising: the plurality of non-symmetric metric memory elements comprising at least one data column of memory cells coupled to have information stored within a data cell, each memory cell including at least one non-volatile memory element programmable to one of the first state of resistance and the second state of resistance; a circuit positioned adjacent the at least one data column, having a net resistance between the first data state and second state states of resistance; and a differential read-out circuit coupled to the at least one data column for differentially comparing a data current generated from the non-symmetric memory element to a reference current generated from the circuit and providing a data output signal, wherein the differential read-out circuit includes the first and second series connected pair of memory elements.

12. The random access memory architecture of claim 10 wherein the voltage bias circuit comprises: a first transistor of a first conductivity type having a first current electrode coupled to the first node, a second current electrode coupled to a second node, and a control electrode coupled to a reference voltage; a second transistor of a second conductivity type having a first current electrode coupled to the second node; a second current electrode coupled to a drain voltage, and a control electrode coupled to the second node; a third transistor of a first conductivity type having a first current electrode coupled to the first node, a second current electrode coupled to the second node, and a control electrode coupled to the reference voltage; and a fourth transistor of the second conductivity type having a first current electrode coupled to the second node, a second current electrode coupled to a drain voltage, and a control electrode coupled to the second node; wherein the first and second series connected pair of memory elements are coupled between the first node and a voltage source.

13. The random access memory architecture of claim 9 further comprising: a third series connected pair of memory elements having a first resistance comprising fifth and sixth memory elements and disposed wherein a current flows in a first direction through both of the third series connected pair of memory element; a fourth series connected pair of memory elements having a second resistance, coupled in parallel with the third series connected pair of memory elements, comprising seventh and eighth memory elements and disposed wherein a current flows in the first direction through both of the fourth series connected pair of memory elements; a second current conductor coupled to a first side of the fifth and seventh memory elements; an eighth transistor coupled between a second side of the fifth memory element and a second node; a ninth transistor coupled between a second side of the seventh memory element and the second node, the second node being coupled to a first side of both the sixth and eighth memory elements; a tenth transistor coupled between a second side of the sixth memory element and the second read bit line; and an eleventh transistor coupled between a second side of the eighth memory element and the second read bit line.

14. The random access memory architecture of claim 8 wherein the first, second, third, and fourth memory elements are each individually capable of having a voltage applied thereacross.

15. The random access memory architecture of claim 8 wherein the first, second, third, and fourth memory elements are each individually capable of having a voltage applied thereacross for setting the state thereof.

16. The random access memory architecture of claim 9 further comprising: a sense amplifier coupled to the first and second read bitlines wherein the sense amplifier is configured to read and set the state of each memory element.

17. The random access memory architecture of claim 7 wherein the first series connected pair of memory elements comprises first and second memory elements and the second series connected pair of memory elements comprises third and fourth memory elements, each of the first, second, third, and fourth memory elements having a first and second terminal, the random access memory architecture further comprises: a current conductor; a first read bit line; a second read bit line; a third read bit line; a first transistor coupled between the current conductor and the first terminal of the first memory element; a second transistor coupled between the current conductor and the first terminal of the third memory element; a third transistor coupled between the second terminal of the first memory element and the first read bit line; a fourth transistor coupled between the second terminal of the third memory element and the second read bit line; a fifth transistor coupled between the first read bitline and the first terminal of the second memory element; a sixth transistor coupled between the second read bitline and the first terminal of the fourth memory element; a seventh transistor coupled between the second terminal of the second memory element and the third read bit line; and an eighth transistor coupled between the second terminal of the fourth memory element and the third read bit line.

18. The random access memory architecture of claim 7 wherein the first series connected pair of memory elements comprise first and second magnetic tunnel junctions and the second series connected pair of memory elements comprise third and fourth magnetic tunnel junctions.

19. A random access memory architecture comprising: an array comprising at least one data column of memory cells coupled to have information stored within at least one memory cell, each memory cell including at least one non- volatile memory element programmable to one of the first state of resistance and the second state of resistance; a midpoint reference coupled between a first node and a second node and having a resistance between that of the first resistance state and the resistance of the second resistance state, comprising: a first memory element coupled to the first node and having a programmable state comprising one of the first resistance state and the second resistance state; a second memory element coupled to the second node and having a programmable state comprising one of the first resistance state and the second resistance state coupled to the first memory cell wherein the first and second memory elements comprise a first series connected pair of elements: a third memory element coupled to the first node and having a programmable state comprising one of the first resistance state and the second resistance state; and a fourth memory element coupled to the second node and having a programmable state comprising one of the first resistance state and the second resistance state coupled to the third memory element, wherein the third and fourth memory elements comprise a second series connected pair of memory elements; and circuitry selectively coupled to either the first or second memory element in order to sense whether the coupled first or second memory element is in the first or second resistance state, and to either the third or fourth memory element in order to sense whether the coupled third or fourth memory element is in the first or second resistance state; a sense amplifier coupled to the array of memory cells; and a voltage bias portion coupled to the sense amplifier, the voltage bias portion including the first, second, third, and fourth memory elements.

20. The random access memory architecture of claim 19 wherein the voltage bias circuit comprises: a first transistor of a first conductivity type having a first current electrode coupled to a first node, a second current electrode coupled to a second node, and a control electrode coupled to a reference voltage; a second transistor of a second conductivity type having a first current electrode coupled to the second node; a second current electrode coupled to a drain voltage, and a control electrode coupled to the second node; a third transistor of a first conductivity type having a first current electrode coupled to the first node, a second current electrode coupled to the second node, and a control electrode coupled to the reference voltage; and a fourth transistor of the second conductivity type having a first current electrode coupled to the second node, a second current electrode coupled to a drain voltage, and a control electrode coupled to the second node; wherein the first and second memory elements are coupled between the first node and a voltage source.