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1. (WO2010074904) RANDOM ACCESS MEMORY ARCHITECTURE INCLUDING MIDPOINT REFERENCE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/074904 International Application No.: PCT/US2009/066405
Publication Date: 01.07.2010 International Filing Date: 02.12.2009
IPC:
G11C 11/00 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Applicants:
EVERSPIN TECHNOLOGIES, INC.; 1300 N. Alma School Road MD:400 Chandler, Arizona 85224, US (AllExceptUS)
NAHAS, Joseph, J. [US/US]; US (UsOnly)
ANDRE, Thomas, W. [US/US]; US (UsOnly)
SUBRAMANIAN, Chitra, K. [US/US]; US (UsOnly)
Inventors:
NAHAS, Joseph, J.; US
ANDRE, Thomas, W.; US
SUBRAMANIAN, Chitra, K.; US
Agent:
KOCH, William E.; Ingrassia, Fisher & Lorenz, P.C. 7010 E. Cochise Rd Scottsdale, Arizona 85253, US
Priority Data:
12/344,33926.12.2008US
Title (EN) RANDOM ACCESS MEMORY ARCHITECTURE INCLUDING MIDPOINT REFERENCE
(FR) ARCHITECTURE DE MÉMOIRE RAM COMPRENANT UNE RÉFÉRENCE DE POINT MILIEU
Abstract:
(EN) A random access memory architecture includes a first series connected pair of memory elements (202, 206, 302, 306, 402, 404) having a first resistance and a second series connected pair of memory elements (204, 208, 304, 308, 406, 408) having a second resistance coupled in parallel with the first series connected pair of memory elements, wherein a current flows in the first direction through both of the first and second series connected pair of memory elements. A sense amplifier (14) is coupled to an array (16) of MRAM cells (77), each including a memory element, and includes a voltage bias portion (12), the voltage bias portion including the first and second series connected pair of memory elements. The memory elements may be, for example, magnetic tunnel junctions.
(FR) Une architecture de mémoire RAM comprend une première paire de d'éléments mémoire connectés en série (202, 206, 302, 306, 402, 404) ayant une première résistance et une seconde paire d'éléments mémoire connectés en série (204, 208, 304, 308, 406, 408) ayant une seconde résistance couplée en parallèle à la première paire d'éléments mémoire connectés en série, un courant circulant dans la première direction à travers l'une des première et seconde paires d'éléments mémoire connectés en série. Un amplificateur de détection (14) est couplé à une matrice (16) de cellules MRAM (77), chacune comprenant un élément mémoire, et comprend une partie de polarisation de tension (12), la partie de polarisation de tension comprenant les première et seconde paires d'éléments mémoire connectés en série. Les éléments mémoire peuvent être, par exemple, des jonctions à tunnel magnétique.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN102265350KR1020110117111