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1. (WO2010074876) ARCHITECTURE FOR ADDRESS MAPPING OF MANAGED NON-VOLATILE MEMORY
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/074876 International Application No.: PCT/US2009/065804
Publication Date: 01.07.2010 International Filing Date: 24.11.2009
IPC:
G06F 12/02 (2006.01) ,G06F 12/06 (2006.01) ,G06F 13/16 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
06
Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
16
for access to memory bus
Applicants:
APPLE INC. [US/US]; 1 Infinite Loop Cupertino, California 95014-2094, US (AllExceptUS)
TOELKES, Tahoma [US/US]; US (UsOnly)
WAKRAT, Nir, Jacob [IL/US]; US (UsOnly)
HERMAN, Kenneth, L. [US/US]; US (UsOnly)
CORLETT, Barry [GB/US]; US (UsOnly)
KHMELNITSKY, Vadim [IL/US]; US (UsOnly)
FAI, Anthony [US/US]; US (UsOnly)
POST, Daniel, Jeffrey [US/US]; US (UsOnly)
THIO, Hsiao [SG/US]; US (UsOnly)
Inventors:
TOELKES, Tahoma; US
WAKRAT, Nir, Jacob; US
HERMAN, Kenneth, L.; US
CORLETT, Barry; US
KHMELNITSKY, Vadim; US
FAI, Anthony; US
POST, Daniel, Jeffrey; US
THIO, Hsiao; US
Agent:
GOTTLIEB, Kirk; Fish & Richardson P.C. P.O. Box 1022 Minneapolis, Minnesota 55440-1022, US
Priority Data:
12/614,36906.11.2009US
61/140,43623.12.2008US
Title (EN) ARCHITECTURE FOR ADDRESS MAPPING OF MANAGED NON-VOLATILE MEMORY
(FR) ARCHITECTURE POUR LA MISE EN CORRESPONDANCE D'ADRESSE D'UNE MÉMOIRE NON VOLATILE GÉRÉE
Abstract:
(EN) The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.
(FR) L'architecture ci-décrite utilise la mise en correspondance d'adresse afin de mettre une adresse en bloc se trouvant sur une interface hôte en correspondance avec une adresse en bloc interne d'un dispositif à mémoire non volatile (non-volatile memory, NVM). L'adresse en bloc est mise en correspondance avec une sélection de circuit interne servant à sélectionner une unité adressable concurremment (CAU) qui est identifiée par l'adresse en bloc. L'architecture ci-décrite prend en charge des commandes de NVM génériques destinées à des opérations d'état de lecture, d'écriture, d'effacement et d'acquisition. Cette architecture prend également en charge une série de commandes étendues afin de prendre en charge des opérations de lecture et d'écriture ayant une influence sur une architecture à CAU multiples.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP2380083JP2012513647CN102326154KR1020110098003