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1. (WO2010074537) CONVOLUTIONAL TURBO CODING METHOD AND DEVICE FOR IMPLEMENTING THE CODING METHOD
Document

Description

Title of Invention

Technical Field

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Background Art

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Disclosure of Invention

Solution to Problem

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Brief Description of Drawings

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Best Mode for Carrying out the Invention

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Claims

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Drawings

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Description

Title of Invention : CONVOLUTIONAL TURBO CODING METHOD AND DEVICE FOR IMPLEMENTING THE CODING METHOD

Technical Field

[1]
The present invention relates to a coding method in a wireless mobile communication system. More particularly, the present invention relates to a Convolutional Turbo Coding (CTC) method and a device for implementing the method.

Background Art

[2]
Mobile Worldwide Interoperability for Microwave Access (WiMAX) is a broadband access technique for implementing “last kilometer” access by using a wireless mode, instead of using a wired mode. It integrates the mobile devices with a fixed broadband network, and provides a convenient and high-speed mobile broadband connection by employing a broadband wireless access technique and a flexible network structure. The WiMAX technique is based on the Institute of Electrical and Electronics Engineers (IEEE) 802.16 standards, which are proposed for microwave and millimeter-wave frequency bands. The mobile WiMAX standard was proposed after the IEEE 802.16d fixed WiMAX standard was proposed. The mobile WiMAX aims to support mobility of the broadband access by building on research started during the standardization of the fixed WiMAX standard. Convolutional Turbo Code (CTC) is a class of Turbo code using several convolution coding schemes. The CTC is incorporated into the IEEE 802.16 and Digital Video Broadcasting - Return Channel via Satellite (DVB-RCS) standards because of its high error correction performance.
[3]
FIG. 1 illustrates a CTC encoder according to the related art. Referring to FIG. 1, the CTC encoder may comprise a 1/3 CTC encoder 101, an interleaver 102 and a puncturing unit 103. As shown in FIG. 1, input information bits are input to the 1/3 CTC encoder 101. Here, the number of encoded output information bits and parity bits is three times the number of information bits. The encoded data is then interleaved by the interleaver 102. The puncturing unit 103 punctures the interleaved data based on the transmission rate, i.e., it chooses the data bits to be transmitted and obtains the encoded bit sequence so as to complete the encoding process.
[4]
More specifically, in the 1/3 CTC encoder 101, a duo binary Circular Recursive Systematic Convolutional (CRSC) code is employed. As shown in FIG. 1, the 1/3 CTC encoder 101 may comprise a CTC interleaver 105 and a constituent encoder 104. Here, the inputs A and B to the CTC interleaver 105 represent the input information bits, which are encoded twice. First, the duo binary CRSC coding is performed on the information bits A and B. That is, a set of information bits A i and B i are simultaneously input to the constituent encoder 104 for encoding, and parity sequences Y 1 and W 1 are obtained. The information bits A and B are also interleaved by the CTC interleaver 105. The second constituent encoding process is then performed to the interleaved sequences. That is, interleaved information bits A j and B j are simultaneously input to the constituent encoder 104 so as to obtain parity sequences Y 2 and W 2. Each code block input into the constituent encoder 104 contains k information bits or N pairs of information bits, i.e., k=2×N, where k is a multiple of 8, and N is a multiple of 4, and 32≤N≤4096.
[5]
As shown in block 106, the interleaver 102 may comprise a symbol separation module, a subblock interleaving module and a symbol grouping module. The symbol separation module is used to allocate the information bits and the encoded bits to 6 subblocks, which are in turn A, B, Y 1, Y 2, W 1 and W 2 described above. The subblock interleaving module is used to interleave these 6 subblocks respectively within each of the subblocks. The interleaving order is the same for each subblock. Assume that after the subblock interleaving is performed respectively to the blocks A, B, Y 1, Y 2, W 1 and W 2, the obtained bit sequences are denoted as A’, B’, Y’ 1, Y’ 2, W’ 1 and W’ 2, then
[6]
A’,B’,Y’ 1,Y’ 2,W’ 1 ,W’ 2
[7]
A’ 0, A’ 1, ……, A’ N-1; B’ 0, B’ 1, ……, B’ N-1; Y’ 1,0, Y’ 1,1, ……, Y’ 1,N-1; Y’ 2,0, Y’ 2,1, ……, Y’ 2,N-1; W’ 1,0, W’ 1,1, ……, W’ 1,N-1; W’ 2,0, W’ 2,1, ……, W’ 2,N-1.
[8]
FIG. 2 illustrates subblock interleaving operations according to the related art. Referring to FIG. 2, a symbol separation module separates encoded bits into subblocks A, B, Y 1, Y 2, W 1 and W 2 in step 201. A subblock interleaving performs an interleaving operation to the subblocks A, B, Y 1, Y 2, W 1 and W 2 in step 202 and a symbol grouping module groups the interleaved subblocks in step 203. Herein, subblocks A and B are output by the symbol grouping module, and the two subblocks Y 1 and Y 2 and the two subblocks W 1 and W 2 are alternately output. After the symbol grouping, the output sequences are A’ 0, A’ 1, ……, A’ N-1; B’ 0, B’ 1, ……, B’ N-1; Y’ 1,0, Y’ 2,0, Y’ 1,1, Y’ 2,1, ……, Y’ 1,N-1, Y’ 2,N-1; W’ 1,0, W’ 2,0, W’ 1,1, W’ 2,1, ……, W’ 1,N-1, W’ 2,N-1.
[9]
In the CTC of the related art, bit reliability in high order modulation is not taken into account. Here, the reliability refers to an average distance between a constellation point of which a certain mapped bit is “0” and a constellation point of which this mapped bit is “1” in a modulation constellation. The larger the distance, the greater the reliability of the mapped bit.
[10]
In a mobile communication system, in order to improve the data transmission rate without any increase of the bandwidth, an M-order Quadrature Amplitude Modulation (M-QAM) scheme may be applied. However, high order modulation is an unequal error protection modulation. For M>4, the respective bits mapped to the M-QAM symbols have different Bit Error Rates (BERs). Inner points of the constellation have less energy and thus may be subject to fading more easily. Accordingly, the bits constituting these symbols are less reliable. In contrast, the bits constituting the points outside the constellation are more reliable.
[11]
FIG. 3 illustrates reliability of bit mapping of high order modulation according to the related art. Referring to FIG. 3, the mapping order of bits is i 1i 2q 1q 2, with i 1=0 and i 1=1 respectively corresponding to the constellation points in the right half plane and in the left half plane, and i 2=0 and i 2=1 respectively corresponding to the constellation points in the middle and at the two sides of the constellation. In this way, the average distance between the constellation points where i 1=1 and where i 1=0 is larger than that corresponding to i 2. Therefore, at the receiving end, i 1 has higher reliability than i 2.
[12]
FIG. 4 illustrates a constituent encoder of a 1/3 CTC encoder implementing duo binary CRSC coding according to the related art. Referring to FIG. 4, when CTC is performed, the input bit A i 401 and the input bit B i 402 are used as a set of inputs to the 1/3 CTC encoder, and the parity bits Y i and W i embody the combined information of the information bit A i and the information bit B i. In this type of duo binary coding, the bit A i and the bit B i should be considered as a whole and treated like a group unit. In the design of the CTC of the related art, if the bit A i is mapped to a bit with high reliability, the bit B i is also mapped to a bit with high reliability. In addition, if the bit A i is mapped to a bit with low reliability, the bit Bi is also mapped to a bit with low reliability. The information bits in the sequence A and the information bits in the sequence B that are simultaneously input to the constituent encoder are said to constitute a bit group. Therefore, from the perspective of the group unit (A i, B i), different group units have unequal bit reliability. Some group units have high reliability whereas some have low reliability.
[13]
Accordingly, there is a problem with the technique of the related art in that combining A i and B i for bit mapping is not taken into account. In addition, there is a problem with the technique of the related art in that the bit reliability of high order modulation is not taken into account during mapping.

Disclosure of Invention

Solution to Problem

[14]
An aspect of the present invention is to address at least the above-mentioned problems and/or disadvantages and to provide at least the advantages described below. According to an aspect of the present invention, a Convolutional Turbo Coding (CTC) method is provided. The method includes the steps of encoding information bits A and B using a constituent encoder, and outputting parity sequences Y 1 and W 1, interleaving the information bits A and B using a CTC interleaver to obtain information bits C and D, and encoding the interleaved information bits C and D using the constituent encoder to obtain parity sequences Y 2 and W 2, interleaving the information bits A and B, the parity sequences Y 1 and W 1 and the parity sequences Y 2 and W 2, respectively, wherein the bits in at least one of a bit group constituted of the information bits A and B, a bit group constituted of the sequences Y 1 and W 1, and a bit group constituted of the sequences Y 2 and W 2 are alternately mapped to bits of constellation points with high reliability and low reliability and puncturing the interleaving result to obtain the encoded bit sequences.
[15]
According to another aspect of the present invention, an apparatus for CTC is provided. The apparatus includes a constituent encoder for encoding information bits A and B and outputting parity sequences Y 1 and W 1, a CTC interleaver for interleaving the information bits A and B to obtain new information bits C and D, and for providing the interleaved information bits C and D to the constituent encoder for encoding to obtain parity sequences Y 2 and W 2, an interleaver for interleaving the information bits A and B, the parity sequences Y 1 and W 1 and the parity sequences Y 2 and W 2, respectively, wherein the bits in at least one of a bit group constituted of the information bits A and B, a bit group constituted of the sequences Y 1 and W 1, and a bit group constituted of the sequences Y 2 and W 2 are alternately mapped to bits of constellation points with high reliability and low reliability, and a puncturing unit for puncturing the output sequences from the interleaver to obtain the encoded bit sequences.
[16]
According to yet another aspect of the present invention, an apparatus for a turbo encoder is provided. The apparatus includes an interleaved information subblock A, an interleaved information subblock B, wherein information subblocks A and B are by-passed, a bit-by-bit multiplexed parity sequence of interleaved Y 1 and Y 2 subblock sequences, the bit-by-bit multiplexed sequence of interleaved Y 1 and Y 2 subblock sequences consisting of a first output bit from a Y 1 subblock interleaver, a first output bit from a Y 2 subblock interleaver, a second output bit from the Y 1 subblock interleaver, and a second output bit from the Y 2 subblock interleaver, and a bit-by-bit multiplexed parity sequence of the interleaved W 2 and W 1 subblock sequences, the bit-by-bit multiplexed sequence of interleaved W 2 and W 1 subblock sequences consisting of a first output bit from a W 2 subblock interleaver, a first output bit from a W 1 subblock interleaver, a second output bit from the W 2 subblock interleaver, and a second output bit from the W 1 subblock interleaver.
[17]
According to still another aspect of the present invention, A i and B i are combined for bit mapping. Furthermore, the bit reliability of high order modulation is taken into account during the mapping so that the reliability of the coding is improved.
[18]
Other aspects, advantages, and salient features of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses exemplary embodiments of the invention.

Brief Description of Drawings

[19]
The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
[20]
FIG. 1 illustrates a Convolutional Turbo Code (CTC) according the related art;
[21]
FIG. 2 illustrates subblock interleaving operations according to the related art;
[22]
FIG. 3 illustrates reliability of bit mapping of high order modulation according to the related art;
[23]
FIG. 4 illustrates a constituent encoder of a 1/3 CTC encoder implementing duo binary Circular Recursive Systematic Convolutional (CRSC) coding according to the related art;
[24]
FIG. 5 illustrates remapping operations according to a first exemplary embodiment of the present invention;
[25]
FIG. 6 illustrates remapping operations according to a second exemplary embodiment of the present invention; and
[26]
FIG. 7 illustrates remapping operations according to a third exemplary embodiment of the present invention.
[27]
Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.

Best Mode for Carrying out the Invention

[28]
The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.
[29]
The terms and words used in the following description and claims are not limited to the bibliographical meanings, but, are merely used by the inventor to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.
[30]
It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a component surface” includes reference to one or more of such surfaces.
[31]
Exemplary embodiments of the present invention provide improvements in a symbol grouping module, such as the interleaver 102 of the Convolutional Turbo Code (CTC) illustrated in FIG. 1. Hereafter, it is assumed that the outputs from the subblock interleaving module in the interleaver are sequences A’, B’, Y’ 1, Y’ 2, W’ 1 and W’ 2.
[32]
According to an exemplary scheme, sequence A’ is mapped first. Then, the corresponding bit in sequence B’ that is input to the CTC encoder simultaneously with each bit in sequence A’ is found. The bit that is input to the CTC encoder simultaneously with A’ i is denoted as B’ j. B’ j is referred to as a group unit corresponding bit of A’ i. Then, sequence B’ is mapped. If A’ i is mapped to a bit with high reliability, its group unit corresponding bit B’ j should be mapped to a bit with low reliability. Also, if A’ i is mapped to a bit with low reliability, its group unit corresponding bit B’ j should be mapped to a bit with high reliability.
[33]
Furthermore, according to a second exemplary scheme, sequence Y’ 1 may be mapped first. Then, the corresponding bit in sequence W’ 1 that is output from the CTC encoder simultaneously with each bit in sequence Y’ 1 is found. The parity bit that is output from the CTC encoder simultaneously with Y’ 1,i is denoted as W’ 1,j. W’ 1,j is referred to as a group unit corresponding unit of Y’ 1,i. Then, sequence W’ 1 is mapped. If Y’ 1,i is mapped to a bit with high reliability, its group unit corresponding bit W’ 1,j should be mapped to a bit with low reliability. Also, if Y’ 1,i is mapped to a bit with low reliability, its group unit corresponding bit W’ 1,j should be mapped to a bit with high reliability. The parity bits in sequence Y’ 1 and the bits in sequence W’ 1, which are simultaneously output from a constituent encoder, constitute a bit group.
[34]
Moreover, according to a third exemplary scheme, sequence Y’ 2 can also be mapped first. Then, the corresponding bit in sequence W’ 2 that is output from the CTC encoder simultaneously with each bit in sequence Y’ 2 is found. The parity bit that is output from the CTC encoder simultaneously with Y’ 2,i is denoted as W’ 2,j. W’ 2,j is referred to as a group unit corresponding bit of Y’ 2,i. Then, sequence W’ 2 is mapped. If Y’ 2,i is mapped to a bit with high reliability, its group unit corresponding bit W’ 2,j should be mapped to a bit with low reliability. Also, if Y’ 2,i is mapped to a bit with low reliability, its group unit corresponding bit W’ 2,j should be mapped to a bit with high reliability. The parity bits in sequence Y’ 2 and the bits in sequence W’ 2, which are simultaneously output from the constituent encoder, constitute a bit group.
[35]
The above three exemplary schemes can be implemented independently, by combining any two of them together, or by combining all of them together. According to a result of a simulation, the least performance gain is obtained by only applying the second or third schemes. If both the second and third schemes are applied, the performance gain increases a little. When only the first scheme is applied, the performance is superior to that obtained by applying both the second and third schemes. If the first, second, and third schemes are applied, the best performance would generally be obtained.
[36]
Based on the Institute of Electrical and Electronics Engineers (IEEE) 802.16e implementation standard, subblock interleaving operations according to an exemplary embodiment of the present invention is described below with reference to FIG. 5.
[37]
FIG. 5 illustrates remapping operations according to a first exemplary embodiment of the present invention.
[38]
In FIG. 5, it is assumed that the outputs from a subblock interleaving module in an interleaver are sequences A’, B’, Y’ 1, Y’ 2, W’ 1 ,W’ 2. Here, A’, B’, Y’ 1, Y’ 2, W’ 1 ,W’ 2 are specifically arranged as A’ 0, A’ 1, ……, A’ N-1; B’ 0, B’ 1, ……, B’ N-1; Y’ 1,0, Y’ 1,1, ……, Y’ 1,N-1; Y’ 2,0, Y’ 2,1, ……, Y’ 2,N-1; W’ 1,0, W’ 1,1, ……, W’ 1,N-1; W’ 2,0, W’ 2,1, ……, W’ 2,N-1.
[39]
Referring to FIG. 5, as shown in block 501, sequence A’ is mapped first. Based on the IEEE 802.16e standard, the corresponding bit in sequence B’ that is input to the CTC encoder simultaneously with A’ i is B’ i. Then, sequence B’ is mapped. If A’ i is mapped to a bit with high reliability, its group unit corresponding bit B’ i should be mapped to a bit with low reliability. Also, if A’ i is mapped to a bit with low reliability, its group unit corresponding bit B’ i should be mapped to a bit with high reliability.
[40]
Of course, the above operations may also be performed to the bit group constituted of sequences Y’ 1 and W’ 1, and the bit group constituted of sequences Y’ 2 and W’ 2, respectively.
[41]
FIG. 6 illustrates remapping operations according to a second exemplary embodiment of the present invention.
[42]
Referring to FIG. 6, sequence Y’ 1 is mapped first. In the IEEE 802.16e standard, the parity bit that is output from the CTC encoder simultaneously with Y’ 1,i is W’ 1,i. Then, sequence W’ 1 is mapped. If Y’ 1,i is mapped to a bit with high reliability, its group unit corresponding bit W’ 1,i should be mapped to a bit with low reliability. Also, if Y’ 1,i is mapped to a bit with low reliability, its group unit corresponding bit W’ 1,i should be mapped to a bit with high reliability.
[43]
Then, sequence Y’ 2 is mapped. Based on the IEEE 802.16e standard, the parity bit that is output from the CTC encoder simultaneously with Y’ 2,i is W’ 2,i. Then, sequence W’ 2 is mapped. If Y’ 2,i is mapped to a bit with high reliability, its group unit corresponding bit W’ 2,i should be mapped to a bit with low reliability. Also, if Y’ 2,i is mapped to a bit with low reliability, its group unit corresponding bit W’ 2,i should be mapped to a bit with high reliability.
[44]
Of course, the operation of alternate mapping may be performed first to the bits in the bit group constituted of sequences A’ and B’, and then to the bit group constituted of sequences Y’ 1 and W’ 1 or the bit group constituted of sequences Y’ 2 and W’ 2, respectively.
[45]
A third exemplary embodiment of the present invention that combines the first and second exemplary embodiments of the present invention is described below with reference to FIG. 7.
[46]
FIG. 7 illustrates remapping operations according to a third exemplary embodiment of the present invention.
[47]
Referring to FIG. 7, sequence A’ can be mapped first. The corresponding bit in sequence B’ that is input to the CTC encoder simultaneously with A’ i is B’ i. Then, sequence B’ is mapped. If A’ i is mapped to a bit with high reliability, its group unit corresponding bit B’ i should be mapped to a bit with low reliability. Also, if the A’ i is mapped to a bit with low reliability, its group unit corresponding bit B’ i should be mapped to a bit with high reliability. Furthermore, as shown in FIG. 7, sequence Y’ 1 is mapped. In the IEEE 802.16e standard, the parity bit that is output from the CTC encoder simultaneously with Y’ 1,i is W’ 1,i. Then, sequence W’ 1 is mapped. If Y’ 1,i is mapped to a bit with high reliability, its group unit corresponding bit W’ 1,i should be mapped to a bit with low reliability. Also, if the Y’ 1,i is mapped to a bit with low reliability, its group unit corresponding bit W’ 1,i should be mapped to a bit with high reliability. Then, sequence Y’ 2 is mapped. In the IEEE 802.16e standard, the parity bit that is output from the CTC encoder simultaneously with Y’ 2,i is W’ 2,i. Then, sequence W’ 2 is mapped. If Y’ 2,i is mapped to a bit with high reliability, its group unit corresponding bit W’ 2,i should be mapped to a bit with low reliability. Also, if the Y’ 2,i is mapped to a bit with low reliability, its group unit corresponding bit W’ 2,i should be mapped to a bit with high reliability.
[48]
In FIG. 7, the bits with high reliability are indicated by the bits to which arrows point. If the bits with high reliability are odd number bits and the bits with low reliability are even number bits as shown in FIG. 7, then the output sequences are A’ 0, A’ 1, ……, A’ N-1; B’ 1, B’ 0, ……, B’ N-1, B’ N-2; Y’ 1,0, Y’ 2,0, Y’ 1,1, Y’ 2,1, ……, Y’ 1,N-1, Y’ 2,N-1; W’ 2,0, W’ 1,0, W’ 2,1, W’ 1,1, ……, W’ 2,N-1, W’ 1,N-1.
[49]
While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

Claims

[Claim 1]
A method for Convolutional Turbo Coding (CTC), the method comprising the steps: a) encoding information bits A and B using a constituent encoder, and outputting parity sequences Y 1 and W 1; b) interleaving the information bits A and B using a CTC interleaver to obtain information bits C and D, and encoding the interleaved information bits C and D using the constituent encoder to obtain parity sequences Y 2 and W 2; c) interleaving the information bits A and B, the parity sequences Y 1 and W 1 and the parity sequences Y 2 and W 2, respectively, wherein the bits in at least one of a bit group comprising the information bits A and B, a bit group comprising the sequences Y 1 and W 1, and a bit group comprising the sequences Y 2 and W 2 are alternately mapped to bits of constellation points with high reliability and low reliability; and d) puncturing the interleaving result to obtain the encoded bit sequences.
[Claim 2]
The method according to claim 1, wherein in the step c), the bit in one sequence and the corresponding bit in the other sequence in the bit group are alternately mapped to the bits of the constellation points with high reliability and low reliability.
[Claim 3]
An apparatus for Convolutional Turbo Coding (CTC), the apparatus comprising: a constituent encoder for encoding information bits A and B and outputting parity sequences Y 1 and W 1; a CTC interleaver for interleaving the information bits A and B to obtain new information bits C and D, and for providing the interleaved information bits C and D to the constituent encoder for encoding to obtain parity sequences Y 2 and W 2; an interleaver for interleaving the information bits A and B, the parity sequences Y 1 and W 1 and the parity sequences Y 2 and W 2, respectively, wherein the bits in at least one of a bit group constituted of the information bits A and B, a bit group constituted of the sequences Y 1 and W 1, and a bit group constituted of the sequences Y 2 and W 2 are alternately mapped to bits of constellation points with high reliability and low reliability; and a puncturing unit for puncturing the output sequences from the interleaver to obtain the encoded bit sequences.
[Claim 4]
The apparatus according to claim 3, wherein the interleaver maps the bit in one sequence and the corresponding bit in the other sequence in the bit group alternately to the bits of the constellation points with high reliability and low reliability.
[Claim 5]
An apparatus for a turbo encoder, the apparatus comprising: an interleaved information subblock A; an interleaved information subblock B, wherein information subblocks A and B are by-passed; a bit-by-bit multiplexed parity sequence of interleaved Y 1 and Y 2 subblock sequences, the bit-by-bit multiplexed sequence of interleaved Y 1 and Y 2 subblock sequences consisting of a first output bit from a Y 1 subblock interleaver, a first output bit from a Y 2 subblock interleaver, a second output bit from the Y 1 subblock interleaver, and a second output bit from the Y 2 subblock interleaver; and a bit-by-bit multiplexed parity sequence of the interleaved W 2 and W 1 subblock sequences, the bit-by-bit multiplexed sequence of interleaved W 2 and W 1 subblock sequences consisting of a first output bit from a W 2 subblock interleaver, a first output bit from a W 1 subblock interleaver, a second output bit from the W 2 subblock interleaver, and a second output bit from the W 1 subblock interleaver.

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