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1. (WO2010074076) SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/074076 International Application No.: PCT/JP2009/071321
Publication Date: 01.07.2010 International Filing Date: 22.12.2009
IPC:
H01L 21/316 (2006.01) ,C23C 14/08 (2006.01) ,H01L 21/31 (2006.01) ,H01L 21/8247 (2006.01) ,H01L 27/115 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/788 (2006.01) ,H01L 29/792 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
314
Inorganic layers
316
composed of oxides or glassy oxides or oxide-based glass
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
14
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
06
characterised by the coating material
08
Oxides
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8246
Read-only memory structures (ROM)
8247
electrically-programmable (EPROM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
788
with floating gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
792
with charge trapping gate insulator, e.g. MNOS-memory transistor
Applicants:
キヤノンアネルバ株式会社 CANON ANELVA CORPORATION [JP/JP]; 神奈川県川崎市麻生区栗木2-5-1 2-5-1 Kurigi, Asao-ku, Kawasaki-shi, Kanagawa 2158550, JP (AllExceptUS)
中川 隆史 NAKAGAWA Takashi [JP/JP]; JP (UsOnly)
金 恩美 KIM Eun-mi [KR/JP]; JP (UsOnly)
北野 尚武 KITANO Naomu [JP/JP]; JP (UsOnly)
真下 公子 MASHIMO Kimiko [JP/JP]; JP (UsOnly)
Inventors:
中川 隆史 NAKAGAWA Takashi; JP
金 恩美 KIM Eun-mi; JP
北野 尚武 KITANO Naomu; JP
真下 公子 MASHIMO Kimiko; JP
Agent:
岡部 正夫 OKABE Masao; 東京都千代田区丸の内3-2-3 富士ビル602号室 No. 602, Fuji Bldg. , 2-3, Marunouchi 3-chome, Chiyoda-ku, Tokyo 1000005, JP
Priority Data:
2008-33169326.12.2008JP
Title (EN) SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS
(FR) PROCÉDÉ DE TRAITEMENT DE SUBSTRAT ET APPAREIL DE TRAITEMENT DE SUBSTRAT
(JA) 基板処理方法及び基板処理装置
Abstract:
(EN) Disclosed are a substrate processing method and a substrate processing apparatus, which are capable of forming a high dielectric film by a sputtering method within one same vacuum chamber, said high dielectric film being that is reduced in oxygen defects and traps by hot carriers.  A substrate processing method according to one embodiment of the present invention comprises: a first step wherein a substrate to be processed (102) arranged within a film-forming chamber (100) is heated, and a metal film is deposited on the substrate to be processed (102) by physical deposition using a target (106); and a second step wherein a gas containing an element that oxidizes the metal film is supplied into the film-forming chamber (100), and the metal film is oxidized within the chamber by thermal oxidation.
(FR) L'invention concerne un procédé de traitement de substrat et un appareil de traitement de substrat qui permettent de former une pellicule fortement diélectrique par un procédé de pulvérisation dans une même chambre à vide, ladite pellicule hautement diélectrique présentant une réduction des défauts d'oxygène et des pièges par les porteurs chauds. Un procédé de traitement de substrat selon un mode de réalisation de la présente invention comprend : une première étape dans laquelle un substrat à traiter (102) disposé dans une chambre de formation de pellicule (100) est chauffé et une pellicule de métal est déposée sur le substrat à traiter (102) par dépôt physique au moyen d'une cible (106) ; et une seconde étape dans laquelle un gaz contenant un élément qui oxyde la pellicule de métal est injecté dans la chambre de formation de pellicule (100) et la pellicule de métal est oxydée dans la chambre par oxydation thermique.
(JA) 本発明は、スパッタ法を用いて酸素欠損やホットキャリアによるトラップの少ない高誘電体膜を、同一の真空容器内で形成可能な基板処理方法及び基板処理装置を提供する。本発明の一実施形態に係る基板処理方法は、成膜処理室(100)内に配した被処理基板(102)を加熱し、ターゲット(106)を用いた物理蒸着により被処理基板(102)に金属膜を堆積する第1の工程と、成膜処理室(100)内で、金属膜を酸化する元素を含有するガスを供給し、熱酸化反応によって金属膜を酸化する第2の工程とを有する。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JP4584356JPWO2010074076US20110312179