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1. (WO2010074061) ROLLED COPPER FOIL OR ELECTROLYTIC COPPER FOIL FOR ELECTRONIC CIRCUIT, AND METHOD FOR FORMING ELECTRONIC CIRCUIT USING THE ROLLED COPPER FOIL OR ELECTROLYTIC COPPER FOIL
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/074061 International Application No.: PCT/JP2009/071293
Publication Date: 01.07.2010 International Filing Date: 22.12.2009
IPC:
H05K 3/06 (2006.01) ,B32B 15/01 (2006.01) ,C23C 28/00 (2006.01) ,C23F 1/02 (2006.01) ,C25D 5/12 (2006.01) ,C25D 7/06 (2006.01) ,H05K 1/09 (2006.01) ,H05K 3/24 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
02
in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
06
the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
15
Layered products essentially comprising metal
01
all layers being exclusively metallic
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
28
Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups C23C2/-C23C26/173
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
F
NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACES; INHIBITING CORROSION OF METALLIC MATERIAL; INHIBITING INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25247
1
Etching metallic material by chemical means
02
Local etching
C CHEMISTRY; METALLURGY
25
ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
D
PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; JOINING WORKPIECES BY ELECTROLYSIS; APPARATUS THEREFOR
5
Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
10
Electroplating with more than one layer of the same or of different metals
12
at least one layer being of nickel or chromium
C CHEMISTRY; METALLURGY
25
ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
D
PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; JOINING WORKPIECES BY ELECTROLYSIS; APPARATUS THEREFOR
7
Electroplating characterised by the article coated
06
Wires; Strips; Foils
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
09
Use of materials for the metallic pattern
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
22
Secondary treatment of printed circuits
24
Reinforcing of the conductive pattern
Applicants:
JX日鉱日石金属株式会社 JX Nippon Mining & Metals Corporation [JP/JP]; 東京都千代田区大手町二丁目6番3号 6-3, Otemachi 2-chome, Chiyoda-ku, Tokyo 1008164, JP (AllExceptUS)
山西 敬亮 YAMANISHI Keisuke [JP/JP]; JP (UsOnly)
神永 賢吾 KAMINAGA Kengo [JP/JP]; JP (UsOnly)
福地 亮 FUKUCHI Ryo [JP/JP]; JP (UsOnly)
Inventors:
山西 敬亮 YAMANISHI Keisuke; JP
神永 賢吾 KAMINAGA Kengo; JP
福地 亮 FUKUCHI Ryo; JP
Agent:
小越 勇 OGOSHI Isamu; 東京都港区虎ノ門3丁目1番10号 第2虎ノ門電気ビル5階 小越国際特許事務所 OGOSHI International Patent Office Daini-Toranomon Denki Bldg., 5F, 3-1-10 Toranomon, Minato-ku, Tokyo 1050001, JP
Priority Data:
2008-33434326.12.2008JP
Title (EN) ROLLED COPPER FOIL OR ELECTROLYTIC COPPER FOIL FOR ELECTRONIC CIRCUIT, AND METHOD FOR FORMING ELECTRONIC CIRCUIT USING THE ROLLED COPPER FOIL OR ELECTROLYTIC COPPER FOIL
(FR) FEUILLE DE CUIVRE ENROULÉE OU FEUILLE DE CUIVRE ÉLECTROLYTIQUE POUR CIRCUIT ÉLECTRONIQUE, ET PROCÉDÉ DE FORMATION D'UN CIRCUIT ÉLECTRONIQUE AU MOYEN DE LA FEUILLE DE CUIVRE ENROULÉE OU FEUILLE DE CUIVRE ÉLECTROLYTIQUE
(JA) 電子回路用の圧延銅箔又は電解銅箔及びこれらを用いた電子回路の形成方法
Abstract:
(EN) Provided is a rolled copper foil or an electrolytic copper foil for an electronic circuit wherein a circuit is formed by etching. The rolled copper foil or the electrolytic copper foil is provided with: a nickel or nickel alloy layer, which is formed on the etching surface of the rolled copper foil or the electrolytic copper foil and has an etching rate lower than that of copper; and a heat-resistant layer, which is formed on the nickel or nickel alloy layer and is composed of zinc, a zinc alloy, an oxide of zinc or an oxide of the zinc alloy. At the time of forming the circuit by etching the copper foil of the copper-plated multilayer board, the target circuit having a uniform circuit width can be formed by eliminating spread etching toward the bottom, a time required for forming the circuit by etching is shortened as much as possible, the thickness of the nickel or nickel alloy layer is reduced as much as possible, discoloration commonly called "burn" is eliminated by suppressing oxidation when heat is applied, and etching performance is improved and generation of a short-circuit and a circuit width failure is eliminated in pattern etching.
(FR) L'invention concerne une feuille de cuivre enroulée ou une feuille de cuivre électrolytique pour un circuit électronique où le circuit est formé par gravure. La feuille de cuivre enroulée ou la feuille de cuivre électrolytique comporte : une couche de nickel ou d'alliage de nickel qui est formée sur la surface de gravure de la feuille de cuivre enroulée ou la feuille de cuivre électrolytique et dont la vitesse de gravure est inférieure à celle du cuivre; et une couche résistante à la chaleur qui est formée sur la couche de nickel ou d'alliage de nickel et est composée de zinc, d'un alliage de zinc, d'un oxyde de zinc ou d'un oxyde de l'alliage de zinc. Au moment de la formation du circuit par gravure de la feuille de cuivre de la carte multicouche plaquée de cuivre, le circuit cible comportant une largeur de circuit uniforme peut être formé en éliminant la gravure étalée vers le bas, le temps requis pour former le circuit par gravure est réduit autant que possible, l'épaisseur de la couche de nickel ou d'alliage de nickel est réduite autant que possible, la décoloration, communément appelée « brûlure » est éliminée en supprimant l'oxydation lorsque la chaleur est appliquée, et la performance de gravure est augmentée et la génération d'un court-circuit et d'un défaut de largeur de circuit est éliminée dans la gravure de motif.
(JA)  エッチングにより回路形成を行う電子回路用の圧延銅箔又は電解銅箔において、該圧延銅箔又は電解銅箔のエッチング面側に形成された銅よりもエッチングレートの低いニッケル又はニッケル合金層、及び該ニッケル又はニッケル合金層上に形成された亜鉛若しくは亜鉛合金又はこれらの酸化物からなる耐熱層を備えていることを特徴とする電子回路用の圧延銅箔又は電解銅箔。銅張り積層板の銅箔をエッチングにより回路形成を行うに際し、エッチングによるダレを防止し、目的とする回路幅の均一な回路を形成でき、エッチングによる回路形成の時間をなるべく短縮すると共に、ニッケル又はニッケル合金層の厚さを極力薄くすること、さらに熱を受けた場合に酸化を抑制し、通称「ヤケ」と言われる変色を防止すると共に、かつパターンエッチングでのエッチング性の向上、ショートや回路幅の不良の発生を防止することを課題とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
EP2373133JPWO2010074061US20110297641CN102265711KR1020110099268MYPI 2011002932