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1. (WO2010073991) SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/073991 International Application No.: PCT/JP2009/071142
Publication Date: 01.07.2010 International Filing Date: 18.12.2009
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
Applicants:
三菱電機株式会社 Mitsubishi Electric Corporation [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP (AllExceptUS)
大塚 健一 OHTSUKA Kenichi; JP (UsOnly)
三浦 成久 MIURA Naruhisa; JP (UsOnly)
中尾 之泰 NAKAO Yukiyasu; JP (UsOnly)
Inventors:
大塚 健一 OHTSUKA Kenichi; JP
三浦 成久 MIURA Naruhisa; JP
中尾 之泰 NAKAO Yukiyasu; JP
Agent:
吉竹 英俊 YOSHITAKE Hidetoshi; 大阪府大阪市中央区城見1丁目4番70号住友生命OBPプラザビル10階 10th floor, Sumitomo-seimei OBP Plaza Bldg., 4-70, Shiromi 1-chome, Chuo-ku, Osaka-shi, Osaka 5400001, JP
Priority Data:
2008-32665823.12.2008JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
(FR) DISPOSITIF SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置およびその製造方法
Abstract:
(EN) Provided are a semiconductor device wherein switching loss is reduced, and a stable movement thereof and the reliability can be ensured; and a method for producing the same.  A gate insulation film (37) is provided over a n-type source region (34), a p-type body region (33), and a depression region (36).  A gate electrode (38) is provided on the gate insulation film (37) so that the gate electrode covers a part of the n-type source region (34), a part of the p-type body region (33), and a part of the depression region (36); and an end of the gate electrode is disposed above the depression region (36).  The gate insulation film (37) is formed so that a thickness tdep thereof at a position corresponding to the end of the gate electrode (38) on the depression region (36) is larger than a thickness tch thereof on the p-type body region (33) which functions as a channel region.
(FR) La présente invention concerne un dispositif semi-conducteur, une perte de commutation étant réduite et un mouvement stable de celui-ci et la fiabilité pouvant être assurés ; et son procédé de fabrication. Un film d'isolation de grille (37) est disposé sur une région de source du type n (34), une région de corps du type p (33) et une région en creux (36). Une électrode de grille (38) est disposée sur le film d'isolation de grille (37) de façon que l'électrode de grille couvre une partie de la région de source du type n (34), une partie de la région de corps du type p (33) et une partie de la région en creux (36) ; et une extrémité de l'électrode de grille est disposée au-dessus de la région en creux (36). Le film d'isolation de grille (37) est formé de façon qu'une épaisseur tdep de celui-ci en une position correspondant à l'extrémité de l'électrode de grille (38) sur la région en creux (36) soit supérieure à une épaisseur tch de celui-ci sur la région de corps du type p (33) qui fonctionne comme une région de canal.
(JA)  本発明は、スイッチング損失の低減を図るとともに、安定した動作が可能であり、信頼性を確保することができる半導体装置およびその製造方法を提供することを目的とする。本発明では、n型ソース領域(34)上、p型ボディ領域(33)上およびデプレッション領域(36)上にわたって、ゲート絶縁膜(37)を設ける。このゲート絶縁膜(37)上に、n型ソース領域(34)の一部分、p型ボディ領域(33)およびデプレッション領域(36)の一部分を覆い、かつデプレッション領域(36)上に端部を有するようにゲート電極(38)を設ける。ゲート絶縁膜(37)は、デプレッション領域(36)上のゲート電極(38)の端部の位置における膜厚tdepが、チャネル領域として機能するp型ボディ領域(33)上における膜厚tchよりも大きくなるように形成する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2010073991