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1. (WO2010073759) POWER SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/073759 International Application No.: PCT/JP2009/061947
Publication Date: 01.07.2010 International Filing Date: 30.06.2009
IPC:
H01L 29/78 (2006.01) ,H01L 27/04 (2006.01) ,H01L 29/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
Applicants:
三菱電機株式会社 Mitsubishi Electric Corporation [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP (AllExceptUS)
中田 修平 NAKATA Shuhei; JP (UsOnly)
渡辺 昭裕 WATANABE Shoyu; JP (UsOnly)
大塚 健一 OTSUKA Kenichi; JP (UsOnly)
三浦 成久 MIURA Naruhisa; JP (UsOnly)
Inventors:
中田 修平 NAKATA Shuhei; JP
渡辺 昭裕 WATANABE Shoyu; JP
大塚 健一 OTSUKA Kenichi; JP
三浦 成久 MIURA Naruhisa; JP
Agent:
吉竹 英俊 YOSHITAKE Hidetoshi; 大阪府大阪市中央区城見1丁目4番70号住友生命OBPプラザビル10階 10th floor, Sumitomo-seimei OBP Plaza Bldg., 4-70, Shiromi 1-chome, Chuo-ku, Osaka-shi, Osaka 5400001, JP
Priority Data:
2008-32888425.12.2008JP
Title (EN) POWER SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR DE PUISSANCE
(JA) 電力用半導体装置
Abstract:
(EN) Disclosed is a power semiconductor device having the following structure.  The power semiconductor device is configured so that a P well region (41) having a large area and a gate electrode (50) are provided so as not to face each other through a gate insulating film (70).  Specifically, the power semiconductor device is characterized in that the P well region (41) having a large area and the gate electrode (50) are provided so as to face each other through a field oxide film (30) having a larger thickness than the gate insulating film (70), or the gate electrode (50) is not provided on the upper part of the gate insulating film (70) when the P well region (41) having a large area is provided on the lower part of the gate insulating film (70).
(FR) L'invention porte sur un dispositif à semi-conducteur de puissance ayant la structure suivante. Le dispositif à semi-conducteur de puissance est configuré de telle sorte qu'une région de puits P (41) ayant une grande superficie et une électrode de grille (50) sont disposées de façon à ne pas se faire face avec un film isolant de grille (70) intercalé. De manière spécifique, le dispositif à semi-conducteur de puissance est caractérisé en ce que la région de puits P (41) ayant une grande superficie et l'électrode de grille (50) sont disposées de façon à se faire face avec un film d'oxyde de champ (30) intercalé ayant une épaisseur supérieure à celle du film isolant de grille (70), ou l'électrode de grille (50) n'est pas disposée sur la partie supérieure du film isolant de grille (70) lorsque la région de puits P (41) ayant une grande superficie est disposée sur la partie inférieure du film isolant de grille (70).
(JA)  本発明は、電力用半導体装置の構造に関し、面積の大きなPウエル領域(41)とゲート電極(50)とがゲート絶縁膜(70)を介して対向しないように、ゲート絶縁膜(70)より厚さの厚いフィールド酸化膜(30)を介して面積の大きなPウエル領域(41)とゲート電極(50)とを対向させるか、下部に面積の大きなPウエル領域(41)を有するゲート絶縁膜(70)の上部にはゲート電極(50)を設けないことを特徴とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2010073759US20110210392CN102265404JP2014103425DE112009004277KR1020110087337
JP2015216400