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1. (WO2010073624) SEMICONDUCTOR DEVICE AND METHOD FOR TESTING THE SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/073624 International Application No.: PCT/JP2009/007125
Publication Date: 01.07.2010 International Filing Date: 22.12.2009
IPC:
H01L 21/822 (2006.01) ,G01R 31/28 (2006.01) ,H01L 21/66 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
66
Testing or measuring during manufacture or treatment
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants:
日本電気株式会社 NEC CORPORATION [JP/JP]; 東京都港区芝五丁目7番1号 7-1, Shiba 5-chome, Minato-ku, Tokyo 1088001, JP (AllExceptUS)
亀田義男 KAMEDA, Yoshio [JP/JP]; JP (UsOnly)
中川源洋 NAKAGAWA, Yoshihiro [JP/JP]; JP (UsOnly)
野口宏一朗 NOGUCHI, Koichiro [JP/JP]; JP (UsOnly)
水野正之 MIZUNO, Masayuki [JP/JP]; JP (UsOnly)
野瀬浩一 NOSE, Koichi [JP/JP]; JP (UsOnly)
Inventors:
亀田義男 KAMEDA, Yoshio; JP
中川源洋 NAKAGAWA, Yoshihiro; JP
野口宏一朗 NOGUCHI, Koichiro; JP
水野正之 MIZUNO, Masayuki; JP
野瀬浩一 NOSE, Koichi; JP
Agent:
速水進治 HAYAMI, Shinji; 東京都品川区西五反田7-9-2 五反田TGビル9階 Gotanda TG Bldg. 9F, 9-2, Nishi-Gotanda 7-chome, Shinagawa-ku, Tokyo 1410031, JP
Priority Data:
2008-33311726.12.2008JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR TESTING THE SAME
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE TEST
(JA) 半導体装置およびそのテスト方法
Abstract:
(EN) A semiconductor device (1) is comprised of a semiconductor wafer (11) on which a plurality of semiconductor chip forming areas (1A) are formed; circuit portions (12) which are provided within the semiconductor chip forming areas (1A) of the semiconductor wafer (11), respectively; control circuit portions (14) which are provided within the semiconductor chip forming areas (1A), respectively, and connected to the circuit portions (12), respectively, to control the electric power supplied to the circuit portions (12); a power supply line (18) connected to the control circuit portions (14); and a reference power line (17) connected to the control circuit portions (14).  In each control circuit portion (14), the voltage of electric power supplied from the power supply line (18) is controlled based on a reference voltage from the reference power line (17).
(FR) L'invention porte sur un dispositif à semi-conducteur (1) qui comprend une tranche semi-conductrice (11) sur laquelle une pluralité de zones de formation de puce semi-conductrice (1A) sont formées ; des parties circuit (12) qui sont formées dans les zones de formation de puce semi-conductrice (1A) de la tranche semi-conductrice (11), respectivement ; des parties circuit de commande (14) qui sont formées dans les zones de formation de puce semi-conductrice (1A), respectivement, et connectées aux parties circuit (12), respectivement, pour commander l'énergie électrique fournie aux parties circuit (12) ; une ligne d'alimentation électrique (18) connectée aux parties circuit de commande (14) ; et une ligne d'alimentation de référence (17) connectée aux parties circuit de commande (14). Dans chaque partie circuit de commande (14), la tension d'alimentation électrique fournie par la ligne d'alimentation électrique (18) est régulée sur la base d'une tension de référence provenant de la ligne d'alimentation de référence (17).
(JA) 半導体装置(1)は、複数の半導体チップ形成領域(1A)が形成された半導体ウェハ(11)と、半導体ウェハ(11)の各半導体チップ形成領域(1A)内に設けられた回路部(12)と、各半導体チップ形成領域(1A)内に設けられるとともに、回路部(12)に接続され、前記回路部(12)に供給される電力を制御する制御回路部(14)と、複数の前記制御回路部(14)に接続される供給電源線(18)と、複数の制御回路部(14)に接続される参照電源線(17)とを有する。各制御回路部(14)では、参照電源線(17)からの参照電圧に基づいて、供給電源線(18)から供給される電力の電圧を制御する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2010073624US20110260747