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1. (WO2010073570) ENCODING METHOD, ENCODER, AND DECODER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/073570 International Application No.: PCT/JP2009/007011
Publication Date: 01.07.2010 International Filing Date: 18.12.2009
IPC:
H03M 13/19 (2006.01) ,H03M 13/23 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
13
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03
Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05
using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
13
Linear codes
19
Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
13
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03
Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
23
using convolutional codes, e.g. unit memory codes
Applicants:
パナソニック株式会社 PANASONIC CORPORATION [JP/JP]; 大阪府門真市大字門真1006番地 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501, JP (AllExceptUS)
村上豊 MURAKAMI, Yutaka; null (UsOnly)
Inventors:
村上豊 MURAKAMI, Yutaka; null
Agent:
鷲田 公一 WASHIDA, Kimihito; 東京都新宿区西新宿1-23-7 新宿ファーストウエスト8階 8th Floor, Shinjuku First West Bldg., 1-23-7, Nishi-Shinjuku, Shinjuku-ku, Tokyo 1600023, JP
Priority Data:
2008-33402826.12.2008JP
Title (EN) ENCODING METHOD, ENCODER, AND DECODER
(FR) PROCÉDÉ DE CODAGE, CODEUR ET DÉCODEUR
(JA) 符号化方法、符号化器及び復号器
Abstract:
(EN) Disclosed is an encoding method to change an encoding rate of an erasure correcting code, while decreasing a circuit scale of an encoder and a decoder. 12k bit (wherein k represents a natural number) which is an encoding output using LDPC-CC with an encoding rate of 1/2, and comprises information and parity, is defined as one cycle. From the one cycle, only the information is arranged in the output order of the encoding output to obtain 6k bit information X6i, X6i+1, X6i+2, X6i+3, X6i+4, X6i+5, ………, X6(i+k-1) X6(i+k-1)+1, X6(i+k-1)+2, X6(i+k-1)+3, X6(i+k-1)+4, and X6(i+k-1)+5. Known information is inserted in 3k pieces of information (Xj) among the 6k bit information, so that when 3k pieces of mutually different j is divided by 3, there is a remainder of 0 regarding k pieces, there is a remainder of 1 regarding k pieces, and there is a remainder of 2 regarding k pieces, to thereby obtain the parity from the information containing the known information. [Numerical formula 1] (Da1+Da2+Da3)X(D)+(Db1+Db2+Db3)P(D)=0 (1-1) (DA1+DA2+DA3)X(D)+(DB1+DB2+DB3)P(D)=0 (1-2) (Dα1+Dα2+Dα3)X(D)+(Dβ1+Dβ2+Dβ3)P(D)=0 (1-3) wherein X(D) is a polynomial expression of the information X; P(D) is a polynomial expression of the parity; a1, a2, a3 are integers (with the proviso that a1≠a2≠a3); b1, b2, b3 are integers (with the proviso that b1≠b2≠b3); A1, A2, A3 are integers (with the proviso that A1≠A2≠A3); B1, B2, B3 are integers (with the proviso that B1≠B2≠B3); α1, α2, α3 are integers (with the proviso that α1≠α2≠α3); β1, β2, β3 are integers (with the proviso that β1≠β2≠β3); and "c%d" represents "a remainder when c is divided by d".
(FR) L'invention porte sur un procédé de codage qui change un rendement de codage d'un code correcteur d'effacement, tout en réduisant une échelle de circuit d'un codeur et d'un décodeur. 12k bits (où k représente un entier naturel), qui sont une sortie de codage utilisant LDPC-CC avec un rendement de codage de 1/2, et comprennent des bits d'informations et de parité, sont définis à chaque cycle. À partir de chaque cycle, seuls les bits d'informations sont agencés dans l'ordre de sortie de la sortie de codage pour obtenir 6k bits d'informations X6i, X6i+1, X6i+2, X6i+3, X6i+4, X6i+5, ………, X6(i+k-1) X6(i+k-1)+1, X6(i+k-1)+2, X6(i+k-1)+3, X6(i+k-1)+4, et X6(i+k-1)+5. Des informations connues sont insérées dans 3k éléments d'informations (Xj) parmi les 6k bits d'informations, de sorte que lorsque 3k éléments ayant des valeurs j mutuellement différentes sont divisés par 3, il existe un reste de 0 concernant k éléments, il existe un reste de 1 concernant k éléments et il existe un reste de 2 concernant k éléments, pour ainsi obtenir les bits de parité à partir des bits d'informations contenant les informations connues. [Formule numérique 1] (Da1+Da2+Da3)X(D)+(Db1+Db2+Db3)P(D)=0 (1-1) (DA1+DA2+DA3)X(D)+(DB1+DB2+DB3)P(D)=0 (1-2) (Dα1+Dα2+Dα3)X(D)+(Dβ1+Dβ2+Dβ3)P(D)=0 (1-3) dans laquelle X(D) est une expression polynomiale de l'information X; P(D) est une expression polynomiale de la parité; a1, a2, a3 sont des entiers (à condition que a1≠a2≠a3); b1, b2, b3 sont des entiers (à condition que b1≠b2≠b3); A1, A2, A3 sont des entiers (à condition que A1≠A2≠A3); B1, B2, B3 sont des entiers (à condition que B1≠B2≠B3); α1, α2, α3 sont des entiers (à condition que α1≠α2≠α3); β1, β2, β3 sont des entiers (à condition que β1≠β2≠β3); et « c%d » représente « un reste de division de c par d ».
(JA)  符号化器及び復号化器の回路規模の低減を図りつつ、消失訂正符号の符号化率を変更する符号化方法を開示する。符号化率1/2のLDPC-CCを用いた符号化出力である情報及びパリティから構成される12k(kは自然数)ビットを1周期とし、1周期から情報のみを符号化出力の出力順に並べた情報X6i、X6i+1、X6i+2、X6i+3、X6i+4、X6i+5、・・・、X6(i+k-1)、X6(i+k-1)+1、X6(i+k-1)+2、X6(i+k-1)+3、X6(i+k-1)+4、X6(i+k-1)+5の6kビットのうち、3k個の情報Xjに、既知情報を挿入する場合に、異なる3k個のjを3で除算した余りのうち、余りが0となる個数がk個となり、余りが1となる個数がk個となり、余りが2となる個数がk個となるように、情報Xjに既知情報を挿入し、既知情報を含む情報から前記パリティを求める。 【数1】 (Da1+Da2+Da3)X(D)+(Db1+Db2+Db3)P(D)=0 ・・・ (1-1) (DA1+DA2+DA3)X(D)+(DB1+DB2+DB3)P(D)=0 ・・・ (1-2) (Dα1+Dα2+Dα3)X(D)+(Dβ1+Dβ2+Dβ3)P(D)=0 ・・・ (1-3) ここで、X(D)は情報Xの多項式表現であり、P(D)はパリティの多項式表現である。また、a1、a2、a3は整数(ただし、a1≠a2≠a3)であり、b1、b2、b3は整数(ただし、b1≠b2≠b3)である。また、A1、A2、A3は整数(ただし、A1≠A2≠A3)であり、B1、B2、B3は整数(ただし、B1≠B2≠B3)である。また、α1、α2、α3は整数(ただし、α1≠α2≠α3)であり、β1、β2、β3は整数(ただし、β1≠β2≠β3)である。また、「c%d」は「cをdで除算した余り」を示す。
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African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2010073570US20110264984CN102265520US20140245110US20150249469US20180287639