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1. (WO2010073399) SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD AND SOFTWARE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/073399 International Application No.: PCT/JP2008/073828
Publication Date: 01.07.2010 International Filing Date: 26.12.2008
IPC:
H01L 21/82 (2006.01) ,G06F 17/50 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
50
Computer-aided design
Applicants:
ルネサスエレクトロニクス株式会社 Renesas Electronics Corporation [JP/JP]; 神奈川県川崎市中原区下沼部1753番地 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 2118668, JP (AllExceptUS)
石川 綾志 ISHIKAWA, Ryoji [JP/JP]; JP (UsOnly)
Inventors:
石川 綾志 ISHIKAWA, Ryoji; JP
Agent:
筒井 大和 TSUTSUI, Yamato; 東京都新宿区新宿2丁目3番10号 新宿御苑ビル3階 筒井国際特許事務所 Tsutsui & Associates, 3F Shinjuku Gyoen Bldg., 3-10, Shinjuku 2-chome, Shinjuku-ku, Tokyo 1600022, JP
Priority Data:
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD AND SOFTWARE
(FR) PROCÉDÉ DE CONCEPTION DE CIRCUIT INTÉGRÉ À SEMI-CONDUCTEURS ET LOGICIEL
(JA) 半導体集積回路の設計方法およびソフトウエア
Abstract:
(EN) It is possible to improve the failure detection ratio in a step for automatically designing a DFT circuit layout as follows. Signal lines of the DFT circuit are integrated by an AND tree circuit (1) or an OR tree circuit instead of an EXOR tree circuit so that an output is received by a flip-flop (2) for observation. If the EXOR tree circuit is used to detect a failure of the DFT circuit when partial circuits outputting signal lines are shared or when the partial circuits have an identical structure, signals cancel one another and there may be a case that a failure of the original partial circuit cannot be detected. This problem can be solved by using the AND tree circuit (1) or the OR tree circuit instead of the EXOR tree circuit.
(FR) Il est possible d'améliorer le rapport de détection de défaillance à une étape de conception automatique d'un agencement de circuit de DFT de la manière suivante. Les lignes de signaux du circuit de DFT sont intégrées par un circuit d'arborescence ET (1) ou un circuit d'arborescence OU au lieu d'un circuit d'arborescence OU exclusif de sorte qu'une sortie soit reçue par une bascule bistable (2) pour observation. Si le circuit d'arborescence OU exclusif est utilisé pour détecter une défaillance du circuit de DFT lorsque des circuits partiels délivrant des lignes de signaux sont partagés ou lorsque les circuits partiels ont une structure identique, les signaux s'annulent mutuellement et il peut exister un cas dans lequel une défaillance du circuit partiel d'origine ne peut pas être détectée. Ce problème peut être résolu en utilisant le circuit d'arborescence ET (1) ou le circuit d'arborescence OU au lieu du circuit d'arborescence OU exclusif.
(JA)  DFT回路のレイアウト自動設計工程における故障検出率を向上するために、DFT回路の信号線をEXOR tree回路の代わりにAND tree回路1またはOR tree回路で集約し、出力を観測用フリップフロップ2で受ける。各信号線を出力する部分回路が共有されていたりする場合や、その部分回路が同じ構造となっていたりする場合にEXOR tree回路を用いてDFT回路の故障検出処理を行うと、信号同士が打ち消しあって、元の部分回路の故障を検出できなくなってしまう場合があるが、EXOR tree回路を用いる代わりにAND tree回路1またはOR tree回路をもちいることにより、そのような不具合を防ぐことができる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2010073399US20110265053