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1. (WO2010073359) PROBER, TESTING APPARATUS, AND METHOD FOR INSPECTING SEMICONDUCTOR CHIP
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/073359 International Application No.: PCT/JP2008/073707
Publication Date: 01.07.2010 International Filing Date: 26.12.2008
IPC:
H01L 21/66 (2006.01) ,G01R 31/28 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
66
Testing or measuring during manufacture or treatment
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
Applicants:
富士通セミコンダクター株式会社 Fujitsu Semiconductor Limited [JP/JP]; 〒2220033 神奈川県横浜市港北区新横浜二丁目10番23 Kanagawa 2-10-23 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa 2220033, JP (AllExceptUS)
田代 一宏 TASHIRO, Kazuhiro [JP/JP]; JP (UsOnly)
Inventors:
田代 一宏 TASHIRO, Kazuhiro; JP
Agent:
岡本 啓三 OKAMOTO, Keizo; 〒1030013 東京都中央区日本橋人形町3丁目11番7号 山西ビル4階 岡本国際特許事務所 Tokyo OKAMOTO PATENT OFFICE Yamanishi Bldg, 4F 11-7, Nihonbashi Ningyo-cho 3-chome Chuo-ku, Tokyo 1030013, JP
Priority Data:
Title (EN) PROBER, TESTING APPARATUS, AND METHOD FOR INSPECTING SEMICONDUCTOR CHIP
(FR) DISPOSITIF DE SONDE, APPAREIL D'ESSAI ET PROCÉDÉ D'INSPECTION D'UNE PUCE À SEMI-CONDUCTEUR
(JA) プローバ、試験装置、及び半導体チップの検査方法
Abstract:
(EN) Provided are a prober, a testing apparatus and a method for inspecting semiconductor chip, by which an electrode pad can be monitored without largely moving a stage. Specifically, a prober (2) is provided with a probe card (10) having a supporting substrate (11) and a probe (13) attached to the supporting substrate (11); a stage (4) for placing a wafer (40) thereon to be measured; a camera (12), which is arranged on the probe card (10) and monitors an electrode pad (44) of a first semiconductor chip (41) formed on the wafer (40); and a stage moving section (3) which moves the position of the stage (4) with respect to the probe card (10).
(FR) L'invention concerne un dispositif de sonde, un appareil d'essai et un procédé d'inspection d'une puce à semi-conducteur, qui permet de surveiller une électrode sans déplacer beaucoup un plateau. Plus spécifiquement, un dispositif de sonde (2) est muni d'une carte sonde (10) comportant un substrat support (11) et une sonde (13) attachée au substrat support (11); d'un plateau (4) sur lequel une plaquette (40) à mesurer est placée; d'une caméra (12) qui est placée sur la carte sonde (10) et qui surveille une électrode (44) d'une première puce à semi-conducteur (41) formée sur la plaquette (40); et d'une section de déplacement du plateau (3) qui déplace la position du plateau (4) par rapport à la carte sonde (10).
(JA) 【課題】プローバ、試験装置、及び半導体チップの検査方法において、ステージを大きく移動させなくても電極パッドを観察できるようにすること。 【解決手段】支持基板11と、支持基板11に取り付けられたプローブ13とを備えるプローブカード10と、被測定ウエハ40を載せるステージ4と、プローブカード10上に設けられ、被測定ウエハ40に形成された第1の半導体チップ41の電極パッド44を観測するカメラ12と、プローブカード10に対するステージ4の位置を移動させるステージ移動部3とを有するプローバ2による。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2010073359