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1. (WO2010072956) SEMICONDUCTOR STRUCTURE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/072956 International Application No.: PCT/FR2009/052620
Publication Date: 01.07.2010 International Filing Date: 18.12.2009
IPC:
H01L 21/762 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
Applicants:
S'TILE [FR/FR]; 6, Rue Marcel Pagnol F-86180 Buxerolles, FR (AllExceptUS)
STRABONI, Alain [FR/FR]; FR (UsOnly)
Inventors:
STRABONI, Alain; FR
Agent:
CABINET BEAUMONT; 1, Rue Champollion F-38000 Grenoble, FR
Priority Data:
085890422.12.2008FR
Title (EN) SEMICONDUCTOR STRUCTURE
(FR) STRUCTURE SEMICONDUCTRICE
Abstract:
(EN) The invention relates to a structure including a first layer made by sintering silicon powders and a second layer made of monocrystalline silicon, and which does or does not include a diffusion barrier layer or an insulation layer between the first and second layers. The invention can be used in the photovoltaic industry and in various fields, such as in the fields of electronics, microelectronics, optics and optoelectronics.
(FR) L'invention concerne une structure comprenant une première couche réalisée par frittage de poudres de silicium et une deuxième couche réalisée en silicium monocristallin, comprenant ou non une couche formant barrière de diffusion ou une couche isolante entre les première et deuxième couches. Application au domaine photovoltaïque et à divers domaines, comme en électronique, microélectronique, optique, opto-électronique.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: French (FR)
Filing Language: French (FR)
Also published as:
EP2368265CN102265391FR2940520