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1. (WO2010056511) TECHNIQUE FOR PROMOTING EFFICIENT INSTRUCTION FUSION
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2010/056511 International Application No.: PCT/US2009/062219
Publication Date: 20.05.2010 International Filing Date: 27.10.2009
IPC:
G06F 9/06 (2006.01) ,G06F 9/22 (2006.01) ,G06F 9/30 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
22
Micro-control or micro-programme arrangements
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
Applicants:
OUZIEL, Ido [IL/IL]; IL (UsOnly)
RAPPOPORT, Lihu [IL/IL]; IL (UsOnly)
VALENTINE, Robert [IL/IL]; IL (UsOnly)
GABOR, Ron [IL/IL]; IL (UsOnly)
RAGHUVANSHI, Pankaj [IN/US]; US (UsOnly)
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95052, US (AllExceptUS)
Inventors:
OUZIEL, Ido; IL
RAPPOPORT, Lihu; IL
VALENTINE, Robert; IL
GABOR, Ron; IL
RAGHUVANSHI, Pankaj; US
Agent:
VINCENT, Lester, J.; Blakely Sokoloff Taylor & Zafman 1279 Oakmead Parkway Sunnyvale, California 94085, US
Priority Data:
12/290,39530.10.2008US
Title (EN) TECHNIQUE FOR PROMOTING EFFICIENT INSTRUCTION FUSION
(FR) TECHNIQUE PERMETTANT DE PROMOUVOIR UNE FUSION D’INSTRUCTIONS EFFICACE
Abstract:
(EN) A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.
(FR) L'invention concerne une technique qui permet une fusion d’instructions efficace à l’intérieur d’un système d’ordinateur. Dans un mode de réalisation, une logique de processeur retarde le traitement d’une deuxième instruction pendant un laps de temps prédéterminé si une première instruction présente dans une file d’attente d’instructions peut fusionner avec la deuxième instruction.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)