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1. (WO2010035379) SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2010/035379 International Application No.: PCT/JP2009/003433
Publication Date: 01.04.2010 International Filing Date: 22.07.2009
IPC:
H01L 21/3205 (2006.01) ,H01L 23/52 (2006.01) ,H01L 25/065 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
Applicants:
パナソニック株式会社 PANASONIC CORPORATION [JP/JP]; 大阪府門真市大字門真1006番地 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501, JP (AllExceptUS)
西尾太一 NISHIO, Taichi; null (UsOnly)
平野博茂 HIRANO, Hiroshige; null (UsOnly)
太田行俊 OTA, Yukitoshi; null (UsOnly)
Inventors:
西尾太一 NISHIO, Taichi; null
平野博茂 HIRANO, Hiroshige; null
太田行俊 OTA, Yukitoshi; null
Agent:
前田弘 MAEDA, Hiroshi; JP
Priority Data:
2008-24877326.09.2008JP
Title (EN) SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE SAME
(FR) DISPOSITIF À SEMI-CONDUCTEURS ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及びその製造方法
Abstract:
(EN) A through hole (14) is formed to penetrate a semiconductor substrate (1) that comprises a first surface (2a), which is the surface on which elements are formed, and a second surface (2b) on the opposite side thereof. An insulating film (13) is formed on the inner wall of the through hole (14), and a conductive part (12) is formed in the through hole (14) on the inside of the insulating film (13). The insulating film (13) is continuously formed on the inner wall of the through hole (14) to the top of the second surface (2b).
(FR) Selon l'invention, un trou traversant (14) est formé pour pénétrer dans un substrat semi-conducteur (1) qui comporte une première surface (2a), qui est la surface sur laquelle des éléments sont formés, et une seconde surface (2b) sur son côté opposé. Un film isolant (13) est formé sur la paroi intérieure du trou traversant (14), et une partie conductrice (12) est formée dans le trou traversant (14) sur l'intérieur du film isolant (13). Le film isolant (13) est formé de façon continue sur la paroi intérieure du trou traversant (14) jusqu'au dessus de la seconde surface (2b).
(JA)  素子形成面である第1の面(2a)及びその反対側の第2の面(2b)を有する半導体基板(1)を貫通するように貫通孔(14)が形成されている。貫通孔(14)の内壁上に絶縁膜(13)が形成されていると共に貫通孔(14)における絶縁膜(13)の内側に導電部(12)が形成されている。絶縁膜(13)は貫通孔(14)の内壁上から第2の面(2b)上まで連続して形成されている。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2010035379