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Machine translation
1. (WO2010032380) OSCILLATING CIRCUIT, DC-DC CONVERTER, AND SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/032380    International Application No.:    PCT/JP2009/004071
Publication Date: 25.03.2010 International Filing Date: 24.08.2009
IPC:
H03L 7/085 (2006.01), H02M 3/00 (2006.01)
Applicants: RICOH COMPANY, LTD. [JP/JP]; 3-6, Nakamagome 1-chome, Ohta-ku, Tokyo 1438555 (JP) (For All Designated States Except US).
MICHIYOSHI, Takashi [JP/JP]; (JP) (For US Only)
Inventors: MICHIYOSHI, Takashi; (JP)
Agent: ITOH, Tadahiko; (JP)
Priority Data:
2008-236402 16.09.2008 JP
Title (EN) OSCILLATING CIRCUIT, DC-DC CONVERTER, AND SEMICONDUCTOR DEVICE
(FR) CIRCUIT OSCILLANT, CONVERTISSEUR CC-CC, ET DISPOSITIF À SEMI-CONDUCTEURS
Abstract: front page image
(EN)The oscillating circuit (100) includes a variable frequency oscillating circuit (10) for generating a clock signal (CK) whose frequency increases in response to an up-signal (UP) and decreases in response to a down-signal (DOWN), the frequency going up and down continuously between an upper-limit frequency and a lower-limit frequency. An up/down control circuit (20) outputs the down-signal when a duration of a low level of the clock signal drops below a first delay time and outputs the up-signal when the duration exceeds a second delay time longer than the first delay time.
(FR)L'invention porte sur un circuit oscillant (100) qui comprend un circuit oscillant à fréquence variable (10) pour générer un signal d'horloge (CK) dont la fréquence augmente en réponse à un signal d'augmentation (UP) et diminue en réponse à un signal de diminution (DOWN), la fréquence augmentant et diminuant de façon continue entre une fréquence limite supérieure et une fréquence limite inférieure. Un circuit de commande d'augmentation/diminution (20) délivre le signal de diminution lorsqu'une durée d'un niveau bas du signal d'horloge chute sous un premier temps de retard et délivre le signal d'augmentation lorsque la durée dépasse un second temps de retard plus long que le premier temps de retard.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)