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Machine translation
1. (WO2010030474) INTERCONNECT STRUCTURES FOR STACKED DIES, INCLUDING PENETRATING STRUCTURES FOR THROUGH-SILICON VIAS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/030474    International Application No.:    PCT/US2009/054313
Publication Date: 18.03.2010 International Filing Date: 19.08.2009
IPC:
H01L 25/065 (2006.01)
Applicants: MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way, P.O. Box 6 Boise, ID 83707-0006 (US) (For All Designated States Except US).
FAY, Owen, R. [US/US]; (US) (For US Only).
FARNWORTH, Warren, M. [US/US]; (US) (For US Only).
HEMBREE, David, R. [US/US]; (US) (For US Only)
Inventors: FAY, Owen, R.; (US).
FARNWORTH, Warren, M.; (US).
HEMBREE, David, R.; (US)
Agent: WECHKIN, John, M.; (US)
Priority Data:
12/209,029 11.09.2008 US
Title (EN) INTERCONNECT STRUCTURES FOR STACKED DIES, INCLUDING PENETRATING STRUCTURES FOR THROUGH-SILICON VIAS
(FR) STRUCTURES D'INTERCONNEXION POUR PUCES EMPILÉES COMPORTANT DES STRUCTURES PÉNÉTRANTES POUR TROUS D'INTERCONNEXION À TRAVERS LE SILICIUM
Abstract: front page image
(EN)Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.
(FR)L'invention concerne des structures d'interconnexion pour puces empilées comportant des structures pénétrantes pour trous d'interconnexion à travers le silicium, ainsi que des systèmes et des procédés associés. Selon un mode de réalisation particulier, un système comprend un premier substrat semi-conducteur comportant un premier matériau de substrat, et une structure pénétrante supportée par le premier substrat semi-conducteur. Le système comprend en outre un second substrat semi-conducteur comportant un second matériau de substrat avec un renfoncement préformé. La structure pénétrante du premier substrat semi-conducteur vient se loger dans le renfoncement du second substrat semi-conducteur, vient en prise mécanique avec le renfoncement, et est fixée au second substrat semi-conducteur.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)