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Machine translation
1. (WO2010027915) CMOS LEVEL SHIFTER CIRCUIT DESIGN
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/027915    International Application No.:    PCT/US2009/055339
Publication Date: 11.03.2010 International Filing Date: 28.08.2009
IPC:
H03K 3/356 (2006.01), H03K 3/012 (2006.01)
Applicants: QUALCOMM Incorporated [US/US]; Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121 (US) (For All Designated States Except US).
CHABA, Ritu [US/US]; (US) (For US Only).
PARK, Dongkyu [KR/US]; (US) (For US Only).
JUNG, ChangHo [US/US]; (US) (For US Only).
YOON, Sei Seung [KR/US]; (US) (For US Only)
Inventors: CHABA, Ritu; (US).
PARK, Dongkyu; (US).
JUNG, ChangHo; (US).
YOON, Sei Seung; (US)
Agent: TALPALATSKY, Sam; (US)
Priority Data:
12/204,147 04.09.2008 US
Title (EN) CMOS LEVEL SHIFTER CIRCUIT DESIGN
(FR) CONCEPTION DE CIRCUIT DE DÉCALAGE DE NIVEAU CMOS
Abstract: front page image
(EN)A level shifting circuit (402) has a pair of assist circuits (404, 40S). The level shifting circuit (402) includes an input point (420), two output points (416/418), a pair of cross-coupled PMOS transistors (412, 414) coupled to the output points (416, 418), and a pair of NMOS transistors (424, 426, 432, 434) coupled between the input and output points (420). Each assist circuit (404, 406) includes a pair of PMOS transistors (424, 426, 432, 434), one responsive (424, 432) to an input applied to the input point (420), the othe (426, 434) r responsive to the drain voltage of one of the NMOS transistors (408, 410). The assist circuit (404, 406) s temporarily weaken the cross-coupled PMOS transistors (412, 414) when an input changes from low to high, or from high to low. The assist circuits also transiently boost the output.
(FR)L'invention porte sur un circuit de décalage de niveau qui comprend une paire de circuits d'assistance. Le circuit de décalage de niveau comprend un point d'entrée, un point de sortie, une paire de transistors PMOS interconnectés couplés au point de sortie, et une paire de transistors NMOS couplés entre les points d'entrée et de sortie. Chaque circuit d'assistance comprend une paire de transistors PMOS, l'un sensible à une entrée appliquée au point d'entrée, l'autre sensible à la tension de drain de l'un des transistors NMOS. Les circuits d'assistance affaiblissent temporairement les transistors PMOS interconnectés lorsqu'une entrée varie d'un niveau bas à un niveau haut, ou d'un niveau haut à un niveau bas. Les circuits d'assistance amplifient également de façon transitoire la sortie.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)