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1. WO2010026956 - SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Publication Number WO/2010/026956
Publication Date 11.03.2010
International Application No. PCT/JP2009/065241
International Filing Date 01.09.2009
IPC
H01L 21/3205 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 23/52 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
CPC
H01L 2224/0401
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
H01L 2224/05093
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05075Plural internal layers
0508being stacked
05085with additional elements, e.g. vias arrays, interposed between the stacked layers
05089Disposition of the additional element
05093of a plurality of vias
H01L 23/5283
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528Geometry or; layout of the interconnection structure
5283Cross-sectional geometry
H01L 23/5286
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528Geometry or; layout of the interconnection structure
5286Arrangements of power or ground buses
H01L 24/05
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
H01L 24/06
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
24Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
06of a plurality of bonding areas
Applicants
  • 日本電気株式会社 NEC CORPORATION [JP]/[JP] (AllExceptUS)
  • 山道 新太郎 YAMAMICHI Shintaro [JP]/[JP] (UsOnly)
  • 堺 淳 SAKAI Jun [JP]/[JP] (UsOnly)
  • 菊池 克 KIKUCHI Katsumi [JP]/[JP] (UsOnly)
  • 古宇田 光 KOUTA Hikaru [JP]/[JP] (UsOnly)
Inventors
  • 山道 新太郎 YAMAMICHI Shintaro
  • 堺 淳 SAKAI Jun
  • 菊池 克 KIKUCHI Katsumi
  • 古宇田 光 KOUTA Hikaru
Agents
  • 工藤 実 KUDOH Minoru
Priority Data
2008-22527002.09.2008JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION DE CELUI-CI.
(JA) 半導体装置及びその製造方法
Abstract
(EN) The semiconductor device is equipped with element wiring (2), element topmost layer wiring (4), a wiring layer (8-10), and bumps (7). The element wiring (2) is provided on a semiconductor substrate (1) that has a semiconductor device through an insulating layer (50). The element topmost layer wiring (4) is provided on the element wiring (2). The wiring layer (8-10) is equipped with a superconnect insulation layer (9) provided on the element topmost layer wiring (4), superconnect vias (8), and superconnect wiring (10). The bumps (7) are provided on the superconnect wiring (10). The element topmost layer wiring (4) is equipped with a signal pad (4s), a power source pad (4v), and a grounding pad (4g). The surface area of the signal pad (4s) is smaller than the surface area of the power source pad (4v) and the grounding pad (4g). Multiple superconnect vias (8) are provided for at least the power source pad (4v) or the grounding pad (4g).
(FR) Le dispositif à semi-conducteur est pourvu d’un circuit de composant (2), d’un circuit (4) constituant l’extrême couche supérieure du composant, de couches de circuits (8-10) et de bosses (7). Le circuit du composant est placé au dessus d’un substrat (1) à semi-conducteurs qui comporte des éléments semi-conducteurs. Entre les deux s’intercale une couche isolante (50). L’extrême couche supérieure du composant (4) est placée au dessus du circuit du composant. Les couches de circuits (8-10) comportent une couche isolante de super connexion (9) placée au dessus du circuit de l’extrême couche supérieure du composant (4), une via de super connexion (8), et un circuit de super connexion (10). Les bosses (7) sont placées au dessus des circuits super connexion (10). Le circuit (4) constituant l’extrême couche supérieure du composant comporte une plage de connexion pour un signal (4s), une plage de connexion pour une source d’électricité (4v), ainsi qu’une plage de connexion pour le sol (4g). La superficie de la plage de connexion pour le signal (4s) est inférieure à celle de la plage de connexion pour le sol. Des via de super connexion sont placées soit sur la plage de connexion pour la source d’électricité (4v), soit sur la plage de connexion pour le sol (4g), et au moins sur l’une ou l’autre.
(JA)  半導体装置は、素子配線(2)と素子最上層配線(4)と配線層(8-10)とバンプ(7)とを具備する。素子配線(2)は、半導体素子を有する半導体基板(1)上に絶縁層(50)を介して設けられる。素子最上層配線(4)は、素子配線(2)上に設けられる。配線層(8-10)は、素子最上層配線(4)上に設けられたスーパーコネクト絶縁層(9)とスーパーコネクトビア(8)とスーパーコネクト配線(10)を備える。バンプ(7)は、スーパーコネクト配線(10)上に設けられる。素子最上層配線(4)は、信号用パッド(4s)と電源用パッド(4v)とグランド用パッド(4g)を備える。信号用パッド(4s)の面積は、電源用パッド(4v)及びグランド用パッド(4g)の面積よりも小さい。電源用パッド(4v)及びグランド用パッド(4g)の少なくとも一つに複数のスーパーコネクトビア(8)が設けられる。
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