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1. (WO2010022970) A SEMICONDUCTOR DEVICE INCLUDING STRESS RELAXATION GAPS FOR ENHANCING CHIP PACKAGE INTERACTION STABILITY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/022970    International Application No.:    PCT/EP2009/006258
Publication Date: 04.03.2010 International Filing Date: 28.08.2009
Chapter 2 Demand Filed:    29.06.2010    
IPC:
H01L 23/58 (2006.01), H01L 21/768 (2006.01), H01L 23/522 (2006.01)
Applicants: ADVANCED MICRO DEVICES, INC. [US/US]; One AMD Place Mail Stop 68 Sunnyvale, CA 94088-3453 (US) (For All Designated States Except US).
GRILLBERGER, Michael [DE/DE]; (DE) (For US Only).
LEHR, Matthias, Uwe [DE/DE]; (DE) (For US Only)
Inventors: GRILLBERGER, Michael; (DE).
LEHR, Matthias, Uwe; (DE)
Agent: PFAU, Anton, K.; Grünecker, Kinkeldey, Stockmair & Schwanhäusser Leopoldstrasse 4 80802 München (DE)
Priority Data:
10 2008 044 984.9 29.08.2008 DE
12/507,348 22.07.2009 US
Title (EN) A SEMICONDUCTOR DEVICE INCLUDING STRESS RELAXATION GAPS FOR ENHANCING CHIP PACKAGE INTERACTION STABILITY
(FR) DISPOSITIF À SEMI-CONDUCTEURS COMPRENANT DES ESPACES DE RELAXATION DE CONTRAINTE POUR OPTIMISER LA STABILITÉ D'INTERACTION DE BOÎTIER DE PUCE
Abstract: front page image
(EN)By dividing a single chip area into individual sub areas (200a, 200b, 200c on the basis of one or more stress relaxation regions 280a, 280b,) a thermally- induced stress in each of the sub areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip (200) may be used compared to conventional strategies.
(FR)La division d'une zone de puce unique en sous-zones individuelles (200a, 200b, 200c sur la base d'au moins une région de relaxation de contrainte 280a, 280b) permet de diminuer une contrainte thermiquement provoquée dans chacune des sous-zones au cours du fonctionnement de circuits intégrés complexes, ce qui permet d'optimiser la fiabilité globale de systèmes de métallisation complexes qui comprennent des matériaux diélectriques à faible k ou un matériau ULK. Par conséquent, un nombre important de couches de métallisation empilées en association avec des dimensions latérales plus importantes de la puce à semi-conducteurs peuvent être utilisées en comparaison aux stratégies classiques.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)