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1. (WO2010022527) METHOD FOR DEPOSITING AN AMORPHOUS SILICON FILM FOR PHOTOVOLTAIC DEVICES WITH REDUCED LIGHT- INDUCED DEGRADATION FOR IMPROVED STABILIZED PERFORMANCE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2010/022527    International Application No.:    PCT/CH2009/000284
Publication Date: 04.03.2010 International Filing Date: 26.08.2009
IPC:
H01L 31/0392 (2006.01), H01L 31/0368 (2006.01), H01L 31/075 (2012.01), H01L 31/20 (2006.01)
Applicants: OERLIKON SOLAR IP AG, TRÜBBACH [CH/CH]; Hauptstrasse 1a CH-9477 Trübbach (CH) (For All Designated States Except US).
BENAGLI, Stefano [CH/CH]; (CH) (For US Only).
BORRELLO, Daniel [CH/CH]; (CH) (For US Only).
VALLAT-SAUVAIN, Evelyne [CH/CH]; (CH) (For US Only).
MEIER, Johannes [CH/CH]; (CH) (For US Only).
KROLL, Ulrich [DE/CH]; (CH) (For US Only)
Inventors: BENAGLI, Stefano; (CH).
BORRELLO, Daniel; (CH).
VALLAT-SAUVAIN, Evelyne; (CH).
MEIER, Johannes; (CH).
KROLL, Ulrich; (CH)
Common
Representative:
OERLIKON SOLAR IP AG, TRÜBBACH [CH/CH]; Hauptstrasse 1a CH-9477 Trübbach (CH)
Priority Data:
61/092,949 29.08.2008 US
Title (EN) METHOD FOR DEPOSITING AN AMORPHOUS SILICON FILM FOR PHOTOVOLTAIC DEVICES WITH REDUCED LIGHT- INDUCED DEGRADATION FOR IMPROVED STABILIZED PERFORMANCE
(FR) PROCÉDÉ DE DÉPÔT D’UN FILM DE SILICIUM AMORPHE POUR DISPOSITIFS PHOTOVOLTAÏQUES POSSÉDANT UNE RÉDUCTION DE LA DÉGRADATION PROVOQUÉE PAR LA LUMIÈRE POUR DES PERFORMANCES AMÉLIORÉES STABILISÉES
Abstract: front page image
(EN)A thin film photovoltaic device on a substrate is being realized by a method for manufacturing a p-i-n junction semiconductor layer stack with a p-type microcrystalline silicon layer, a p-type amorphous silicon layer, a buffer silicon layer comprising preferably intrinsic amorphous silicon, an intrinsic type amorphous silicon layer, and an n-type silicon layer over the intrinsic type amorphous silicon layer.
(FR)La présente invention concerne un dispositif photovoltaïque à film mince sur un substrat réalisé grâce à un procédé de fabrication d’une pile de couches à semi-conducteur de jonction p-i-n avec une couche de silicium microcristallin de type p, une couche de silicium amorphe de type p, une couche de silicium tampon qui comprend de préférence du silicium amorphe intrinsèque, une couche de silicium amorphe de type intrinsèque, et une couche de silicium de type n sur la couche de silicium amorphe de type intrinsèque.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PE, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)