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1. WO2010010164 - PROCESSOR CIRCUIT WITH SHARED MEMORY

Publication Number WO/2010/010164
Publication Date 28.01.2010
International Application No. PCT/EP2009/059524
International Filing Date 23.07.2009
IPC
G06F 13/16 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 1/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
10Distribution of clock signals
CPC
G06F 13/1684
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
1684using multiple buses
G06F 13/1689
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
1689Synchronisation and timing concerns
Y02D 10/00
YSECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
10Energy efficient computing, e.g. low power processors, power management or thermal management
Applicants
  • EM MICROELECTRONIC-MARIN SA [CH]/[CH] (AllExceptUS)
  • THÉODULOZ, Yves [CH]/[CH] (UsOnly)
  • JAEGGI, Hugo [CH]/[CH] (UsOnly)
  • TOTH, Tomas [SK]/[SK] (UsOnly)
Inventors
  • THÉODULOZ, Yves
  • JAEGGI, Hugo
  • TOTH, Tomas
Agents
  • RAVENEL, T.
Priority Data
01177/0825.07.2008CH
Publication Language French (FR)
Filing Language French (FR)
Designated States
Title
(EN) PROCESSOR CIRCUIT WITH SHARED MEMORY
(FR) CIRCUIT PROCESSEUR À MÉMOIRE PARTAGÉE
Abstract
(EN)
The invention relates to a processor circuit (1) that comprises a computation unit (2), a first memory element (3) for storing data and a second memory element (4) for storing instructions. The first and second memory elements (3, 4) are each connected by a communication bus (5, 6) to the computation unit. The first and second memory elements define a single memory unit (7) in order to define a memory of the shared type. A blocking signal (S-block) acts on the computation unit (2) in order to block the operation thereof.
(FR)
Le circuit processeur (1) comprend une unité de calcul (2), un premier élément mémoire (3) pour le stockage des données et un second élément mémoire (4) pour le stockage des instructions. Lesdits premier et second éléments mémoires (3, 4) sont reliés chacun par un bus de communication (5, 6) à l'unité de calcul. Les premier et deuxième éléments mémoires forment une seule unité mémoire (7) pour réaliser une mémoire du type mémoire partagée. Un signal de blocage (S-block) agit sur l'unité de calcul (2) afin de bloquer son fonctionnement.
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