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1. WO2010005661 - EFFICIENT IN-BAND RELIABILITY WITH SEPARATE CYCLIC REDUNDANCY CODE FRAMES

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[ EN ]

CLAIMS

What is claimed is:

1. A method comprising: generating an error bit checksum to cover transmission errors for a plurality of data bits; framing the plurality of data bits in a write data frame; transferring the write data frame to a dynamic random access memory (DRAM) device via one or more lanes of a data interconnect; framing the error bit checksum in a write error bit frame; and transferring the write error bit frame to the DRAM device via the one or more lanes of the data interconnect.

2. The method of claim 2, further comprising: receiving an indication that a transmission error associated with the data frame was detected based, at least in part, on the error bit checksum; and resending the data frame to the DRAM device.

3. The method of claim 1 , further comprising: issuing a first write command indicating that the write data frame is to be written to the DRAM device; and issuing a second write command indicating that the error bit frame is to be written to the DRAM device.

4. The method of claim 1, further comprising: issuing a single write command indicating that the write data frame and the error bit frame are to be written to the DRAM device.

5. The method of claim 1 , further comprising: receiving a read data frame from the DRAM device, the read data frame including a plurality of read data bits; and receiving a read error bit frame from the DRAM device, wherein the read error bit frame includes a checksum covering at least some of the plurality of read data bits.

6. An integrated circuit comprising: error bit generation logic having as an input a plurality of write data bits to be transferred to a dynamic random access memory (DRAM) device and having as an output a write checksum to cover the plurality of write data bits; and a framing unit to frame a write data frame based on the write data bits and a write error bit frame based on the write checksum.

7. The integrated circuit of claim 6, further comprising: command logic to issue write commands to the DRAM device, wherein the command logic is capable of issuing a write data command to indicate that a data frame is being written to memory and a write error bits command to indicate that a write error bit frame is being written to the DRAM device.

8. The integrated circuit of claim 7, wherein the command logic is capable of issuing a single write command to indicate that both a data frame and an error bit frame are being written to the DRAM device.

9. The integrated circuit of claim 6, further comprising: a receive framing unit to receive a read data frame and a read error bit frame from the DRAM device, wherein the read data frame includes a plurality of read data bits and the read error bit frame includes a checksum covering at least a portion of the plurality of read data bits; logic to generate a local checksum based, at least in part, on the plurality of read data bits; and comparison logic to compare the local checksum with the local checksum.

10. The integrated circuit of claim 9, further comprising: command logic to issue read commands to the DRAM device, wherein the command logic is capable of issuing a read data command to indicate that the read data frame is being read from memory and a read error bits command to indicate that the read error bit frame is being read from the DRAM device.

11. A system comprising: a host including, error bit generation logic having as an input a plurality of write data bits to be transferred to a dynamic random access memory (DRAM) device and having as an output a write checksum to cover the plurality of write data bits, and a framing unit to frame a write data frame based on the write data bits and a write error bit frame based on the write checksum; and a dynamic random access memory (DRAM) device coupled to the host via a memory interconnect.

12. The system of claim 11 , wherein the host further includes command logic to issue write commands to the DRAM device, wherein the command logic is capable of issuing a write data command to indicate that a data frame is being written to memory and a write error bits command to indicate that a write error bit frame is being written to the DRAM device.

13. The system of claim 12, wherein the command logic is capable of issuing a single write command to indicate that both a data frame and an error bit frame are being written to the DRAM device.

14. The system of claim 11 , wherein the host further includes a receive framing unit to receive a read data frame and a read error bit frame from the DRAM device, wherein the read data frame includes a plurality of read data bits and the read error bit frame includes a checksum covering at least a portion of the plurality of read data bits; logic to generate a local checksum based, at least in part, on the plurality of read data bits; and comparison logic to compare the local checksum with the checksum.

15. The system of claim 14, wherein the host further includes command logic to issue read commands to the DRAM device, wherein the command logic is capable of issuing a read data command to indicate that the read data frame is being read from memory and a read error bits command to indicate that the read error bit frame is being read from the DRAM device.