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1. (WO2009128133) ANTIFERROELECTRIC GATE TRANSISTOR AND MANUFACTURING METHOD THEREOF, AND NON-VOLATILE MEMORY ELEMENT
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2009/128133    International Application No.:    PCT/JP2008/057288
Publication Date: 22.10.2009 International Filing Date: 14.04.2008
IPC:
H01L 21/8246 (2006.01), H01L 27/105 (2006.01), H01L 29/78 (2006.01)
Applicants: FUJITSU LIMITED [JP/JP]; 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi, Kanagawa, 2118588 (JP) (For All Designated States Except US).
SATO, Keisuke [JP/JP]; (JP) (For US Only).
KURIHARA, Kazuaki [JP/JP]; (JP) (For US Only).
MARUYAMA, Kenji [JP/JP]; (JP) (For US Only)
Inventors: SATO, Keisuke; (JP).
KURIHARA, Kazuaki; (JP).
MARUYAMA, Kenji; (JP)
Agent: ITOH, Tadahiko; 32nd Floor, Yebisu Garden Place Tower, 20-3, Ebisu 4-chome, Shibuya-ku, Tokyo 1506032 (JP)
Priority Data:
Title (EN) ANTIFERROELECTRIC GATE TRANSISTOR AND MANUFACTURING METHOD THEREOF, AND NON-VOLATILE MEMORY ELEMENT
(FR) TRANSISTOR À GRILLE ANTIFERROÉLECTRIQUE ET PROCÉDÉ DE FABRICATION ASSOCIÉ, ET MÉMOIRE NON VOLATILE
(JA) 反強誘電体ゲートトランジスタおよびその製造方法、不揮発性メモリ素子
Abstract: front page image
(EN)An antiferroelectric gate transistor is used instead of a ferroelectric gate transistor. The antiferroelectric gate transistor comprises a silicon substrate, an antiferroelectric film of a perovskite structure with residual polarization formed over the silicon substrate via a gate insulating film, a gate electrode formed over the antiferroelectric film with the residual polarization and diffusion regions formed within the silicon substrate on a first side of the gate electrode and on a second side opposite to the first side.
(FR)Un transistor à grille antiferroélectrique est utilisé à la place d’un transistor à grille ferroélectrique. Le transistor à grille antiferroélectrique comprend un substrat en silicium, un film antiferroélectrique à structure pérovskite à polarisation résiduelle, formé par-dessus le substrat en silicium via un film isolant de grille, une électrode grille formée par-dessus le film antiferroélectrique, les zones de polarisation résiduelle et de diffusion étant formées dans le substrat en silicium sur un premier côté de l’électrode grille et sur un second côté opposé au premier côté.
(JA) 強誘電体ゲートトランジスタの代わりに、反強誘電体ゲートトランジスタを使い、前記反強誘電体ゲートトランジスタは、シリコン基板と、前記シリコン基板上にゲート絶縁膜を介して形成された、残留分極を有するペロブスカイト構造の反強誘電体膜と、前記残留分極を有する反強誘電体膜上に形成されたゲート電極と、前記シリコン基板中、前記ゲート電極の第1の側、および前記第1の側の反対の第2の側に形成された、拡散領域と、を含む。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)