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1. (WO2009126267) PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION

Pub. No.:    WO/2009/126267    International Application No.:    PCT/US2009/002188
Publication Date: Oct 15, 2009 International Filing Date: Apr 7, 2009
IPC: H04L 12/56
Applicants: ALTERA CORPORATION
CHAN, Allen
SHUMARAYEV, Sergey
WONG, Wilson
DING, Weiqi
Inventors: CHAN, Allen
SHUMARAYEV, Sergey
WONG, Wilson
DING, Weiqi
Title: PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION
Abstract:
An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.