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1. (WO2009121045) ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS

Pub. No.:    WO/2009/121045    International Application No.:    PCT/US2009/038705
Publication Date: Oct 1, 2009 International Filing Date: Mar 28, 2009
IPC: H04L 1/00
Applicants: QUALCOMM INCORPORATED
CHALLA, Raghu, N.
SAMPATH, Hemanth
ROSTAMPISHEH, Ali
Inventors: CHALLA, Raghu, N.
SAMPATH, Hemanth
ROSTAMPISHEH, Ali
Title: ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS
Abstract:
An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memory segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.