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1. (WO2009120981) VECTOR INSTRUCTIONS TO ENABLE EFFICIENT SYNCHRONIZATION AND PARALLEL REDUCTION OPERATIONS

Pub. No.:    WO/2009/120981    International Application No.:    PCT/US2009/038596
Publication Date: Oct 1, 2009 International Filing Date: Mar 27, 2009
IPC: G06F 9/38
G06F 9/445
G06F 15/80
Applicants: INTEL CORPORATION
SMELYANSKIY, Mikhail
KUMAR, Sanjeev
KIM, Daehyun
LEE, Victor, W.
NGUYEN, Anthony, D.
CHEN, Yen-Kuang
HUGHES, Christopher
KIM, Changkyu
CHHUGANI, Jatin
Inventors: SMELYANSKIY, Mikhail
KUMAR, Sanjeev
KIM, Daehyun
LEE, Victor, W.
NGUYEN, Anthony, D.
CHEN, Yen-Kuang
HUGHES, Christopher
KIM, Changkyu
CHHUGANI, Jatin
Title: VECTOR INSTRUCTIONS TO ENABLE EFFICIENT SYNCHRONIZATION AND PARALLEL REDUCTION OPERATIONS
Abstract:
In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.