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Machine translation
1. (WO2009063596) RECONFIGURABLE CIRCUIT, RESET METHOD, AND CONFIGURATION INFORMATION GENERATION DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2009/063596    International Application No.:    PCT/JP2008/003121
Publication Date: 22.05.2009 International Filing Date: 30.10.2008
IPC:
H03K 19/173 (2006.01), G06F 1/24 (2006.01)
Applicants: PANASONIC CORPORATION [JP/JP]; 1006, Oaza Kadoma, Kadoma-shi, Osaka 5718501 (JP) (For All Designated States Except US).
MORIMOTO, Takashi; (For US Only).
NISHIOKA, Shinichiro; (For US Only).
ASAI, Koji; (For US Only)
Inventors: MORIMOTO, Takashi; .
NISHIOKA, Shinichiro; .
ASAI, Koji;
Agent: NAKAJIMA, Shiro; 6F, Yodogawa 5-Bankan 2-1, Toyosaki 3-chome, Kita-ku Osaka-shi, Osaka 5310072 (JP)
Priority Data:
2007-292829 12.11.2007 JP
Title (EN) RECONFIGURABLE CIRCUIT, RESET METHOD, AND CONFIGURATION INFORMATION GENERATION DEVICE
(FR) CIRCUIT RECONFIGURABLE, PROCÉDÉ DE RÉINITIALISATION, ET DISPOSITIF DE GÉNÉRATION D'INFORMATIONS DE CONFIGURATION
(JA) 再構成可能回路、リセット方法、及び構成情報生成装置
Abstract: front page image
(EN)Provided is a reconfigurable circuit which includes a plurality of reconfigurable cells and modifies the configuration of the calculation processing unit contained in each of the reconfigurable cells. Each of the reconfigurable cells has: a calculation storage unit which holds the calculation result obtained by the calculation processing unit; a flag holding unit which holds a reset flag indicating whether the calculation storage unit can be reset; and a reset control unit which controls reset of the calculation storage unit by using the flag held in the flag holding unit when modifying the configuration of the calculation processing unit.
(FR)L'invention concerne un circuit reconfigurable qui comprend une pluralité de cellules reconfigurables et modifie la configuration de l'unité de calcul contenue dans chacune des cellules reconfigurables. Chacune des cellules reconfigurables possède : une unité de stockage de calculs qui conserve le résultat du calcul obtenu par l'unité de calcul ; une unité de conservation de repères qui conserve un repère de réinitialisation qui indique si l'unité de stockage de calculs peut être réinitialisée ; et une unité de commande de réinitialisation qui contrôle la réinitialisation de l'unité de stockage de calculs en utilisant le repère conservé dans l'unité de conservation de repères lors de la modification de la configuration de l'unité de calcul.
(JA) 本発明は、複数の再構成セルを含み、各再構成セルに含まれる演算処理部の構成を変更する再構成可能回路であって、前記各再構成セルは、前記演算処理部による演算結果を保持する演算記憶部と、前記演算記憶部のリセットの要否を示すリセットフラグを保持しているフラグ保持部と、前記演算処理部の構成変更時に、前記フラグ保持部に保持されているフラグを用いて、前記演算記憶部のリセットを制御するリセット制御部とを備えることを特徴とする。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)