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Machine translation
1. (WO2009063373) SIGNAL PROCESSOR COMPRISING AN AMPLIFIER
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2009/063373    International Application No.:    PCT/IB2008/054667
Publication Date: 22.05.2009 International Filing Date: 07.11.2008
IPC:
H03F 3/45 (2006.01)
Applicants: NXP B.V. [NL/NL]; High Tech Campus 60 NL-5656 AG Eindhoven (NL) (For All Designated States Except US).
BRUIN, Paulus, P., F., M. [NL/NL]; (NL) (For US Only)
Inventors: BRUIN, Paulus, P., F., M.; (NL)
Agent: WILLIAMSON, Paul, L.; NXP B.V. IP & L Department Betchworth House 57-65 Station Road Redhill, Surrey RH1 1DL (GB)
Priority Data:
07120440.8 12.11.2007 EP
Title (EN) SIGNAL PROCESSOR COMPRISING AN AMPLIFIER
(FR) PROCESSEUR DE SIGNAUX COMPRENANT UN AMPLIFICATEUR
Abstract: front page image
(EN)An amplifier (A1) within a signal processor comprises a pair of complementary differential pairs (DP1, DP2) in the sense that one differential pair comprises transistors having a polarity opposite to that of transistors in the other differential pair. The one and the other differential pair commonly receive a differential input signal, which has a common mode component. A current combining circuit (CC) combines output currents of the one and the other differential pair so as to obtain an output current that varies as a function of the differential input signal. The one and the other differential pair each have a biasing circuit (R1, R2), which provides a tail current that varies with the common mode component in a substantially linear fashion.
(FR)L'amplificateur (Al) d'un processeur de signaux comprend une paire de paires différentielles complémentaires (DPI, DP2) en ce sens qu'une paire différentielle comprend des transistors de polarité opposée à celle des transistors de l'autre paire différentielle. L'une et l'autre paires différentielles reçoivent en commun un signal d'entrée différentiel présentant un composant de mode commun. Un circuit combinateur combine les courants de sortie de l'une et l'autre paires différentielles afin d'obtenir un courant de sortie qui varie en fonction du signal différentiel introduit. Chacune des paires différentielles présente un circuit de polarisation (Rl, R2), qui fournit un courant de queue qui varie avec la composante de mode commun de manière sensiblement linéaire.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)