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Machine translation
1. (WO2009061835) METHODS AND APPARATUSES FOR SELECTABLE VOLTAGE SUPPLY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2009/061835    International Application No.:    PCT/US2008/082504
Publication Date: 14.05.2009 International Filing Date: 05.11.2008
IPC:
H03K 17/693 (2006.01), H03K 17/16 (2006.01), H03K 17/0814 (2006.01)
Applicants: QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121-1714 (US) (For All Designated States Except US).
CASSIA, Marco [IT/US]; (US) (For US Only).
HADJICHRISTOS, Aristotele [US/US]; (US) (For US Only).
DONOVAN, Conor [IE/US]; (US) (For US Only).
LEE, Sang-oh [KR/US]; (US) (For US Only)
Inventors: CASSIA, Marco; (US).
HADJICHRISTOS, Aristotele; (US).
DONOVAN, Conor; (US).
LEE, Sang-oh; (US)
Agent: HOOKS, William M.; ATTN: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121-1714 (US)
Priority Data:
11/935,186 05.11.2007 US
Title (EN) METHODS AND APPARATUSES FOR SELECTABLE VOLTAGE SUPPLY
(FR) ALIMENTATIONS DE TENSION À NIVEAU COMMUTABLE POUR DES COMMUNICATIONS MULTIMODALES
Abstract: front page image
(EN)A circuit which selects a supply voltage from a plurality of voltage supplies is presented. The circuit includes a first transistor (215) configured to select a first voltage supply (240), a second transistor (210) configured to select a second voltage supρly (230), a first parasitic current inhibitor (205) coupled the first transistor, (215) the first voltage supply, (240) and the second voltage supply, (230) where the first parasitic current inhibitor (205) automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the first transistor (215), and a second parasitic current inhibitor (207) coupled the second transistor (210), the first voltage supply (240), and the second voltage supply(230), where the second parasitic current inhibitor (207) automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the second transistor (210).
(FR)L'invention concerne un circuit qui sélectionne une tension d'alimentation à partir d'une pluralité d'alimentations de tension. Le circuit comprend un premier transistor configuré pour sélectionner une première alimentation de tension, un second transistor configuré pour sélectionner une seconde alimentation de tension, un premier inhibiteur de courant parasite relié au premier transistor, à la première alimentation de tension et à la seconde alimentation de tension, le premier inhibiteur de courant parasite utilisant automatiquement l'alimentation de tension fournissant la tension la plus élevée pour empêcher qu'un courant de substrat ne circule à travers un nœud de masse du premier transistor, et un second inhibiteur de courant parasite relié au second transistor, à la première alimentation de tension et à la seconde alimentation de tension, le second inhibiteur de courant parasite utilisant automatiquement l'alimentation de tension fournissant la tension la plus élevée pour empêcher qu'un courant de substrat ne s'écoule à travers un nœud de masse du second transistor.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)