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Machine translation
1. (WO2009060533) DATA TRANSFER CIRCUIT AND ITS ADJUSTING METHOD
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2009/060533    International Application No.:    PCT/JP2007/071798
Publication Date: 14.05.2009 International Filing Date: 09.11.2007
IPC:
H04L 25/03 (2006.01), H03K 19/0175 (2006.01)
Applicants: FUJITSU LIMITED [JP/JP]; 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi, Kanagawa 2118588 (JP) (For All Designated States Except US).
TSUZUKI, Toshihide [JP/JP]; (JP) (For US Only).
INOUE, Hirotoshi [JP/JP]; (JP) (For US Only)
Inventors: TSUZUKI, Toshihide; (JP).
INOUE, Hirotoshi; (JP)
Agent: YOKOYAMA, Junichi; c/o FUJITSU LIMITED, 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi, Kanagawa 2118588 (JP)
Priority Data:
Title (EN) DATA TRANSFER CIRCUIT AND ITS ADJUSTING METHOD
(FR) CIRCUIT DE TRANSFERT DE DONNÉES ET SON PROCÉDÉ DE RÉGLAGE
(JA) データ転送回路及びその調整方法
Abstract: front page image
(EN)A data transfer circuit comprises a buffer circuit having a first output circuit for outputting a signal and a first input circuit which is inputted with a signal, a test circuit having a second output circuit for outputting an input signal and a second input circuit for outputting a signal inputted from the second output circuit, and an adjustment circuit which provides a signal to the second output circuit of the test circuit and adjusts the output of the first output circuit of the buffer circuit based on the signal output from the second input circuit of the test circuit. Due to this structure, an output driver can be adjusted without controlling the transmitting and receiving direction of a signal of a bidirectional buffer.
(FR)L'invention concerne un circuit de transfert de données comprenant un circuit tampon comportant un premier circuit de sortie destiné à délivrer un signal et un premier circuit d'entrée recevant un signal ; un circuit de test comportant un deuxième circuit de sortie destiné à délivrer un signal d'entrée et un deuxième circuit d'entrée destiné à délivrer un signal reçu du deuxième circuit de sortie ; et un circuit de réglage qui délivre un signal au deuxième circuit de sortie du circuit de test et règle la sortie du premier circuit de sortie du circuit tampon en fonction du signal délivré par le deuxième circuit d'entrée du circuit de test. Cette structure permet de régler un circuit d'attaque de sortie sans commande du sens de transmission et de réception d'un signal d'un tampon bidirectionnel.
(JA) 本発明は、データ転送回路は、信号を出力する第一の出力回路と、信号が入力する第一の入力回路とを有するバッファ回路と、入力する信号を出力する第二の出力回路と、該第二の出力回路から入力する信号を出力する第二の入力回路とを有する試験回路と、該試験回路の該第二の出力回路に信号を入力し、該試験回路の該第二の入力回路から出力される信号に基づいて、該バッファ回路の該第一の出力回路の出力を調整する調整回路とを有することを特徴とする。そのため、双方向バッファの信号の送受信方向の制御を行うことなく出力ドライバの調整を行うことができる。
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)