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Machine translation
1. (WO2009058532) METHODS FOR FABRICATING SUB-RESOLUTION ALIGNMENT MARKS ON SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES INCLUDING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2009/058532    International Application No.:    PCT/US2008/079209
Publication Date: 07.05.2009 International Filing Date: 08.10.2008
IPC:
H01L 21/60 (2006.01)
Applicants: MICRON TECHNOLOGY, INC. [US/US]; Mail Stop 525 8000 South Federal Way Boise, ID 83707-0006 (US) (For All Designated States Except US).
PRATT, David, S. [US/US]; (US) (For US Only).
SULFRIDGE, Marc, A. [US/US]; (US) (For US Only)
Inventors: PRATT, David, S.; (US).
SULFRIDGE, Marc, A.; (US)
Agent: HAMER, Katherine, A.; Traskbritt, 230 South 500 East, Suite 300, P. O. Box 2550, Salt Lake City, UT 84110-2550 (US)
Priority Data:
11/926,619 29.10.2007 US
Title (EN) METHODS FOR FABRICATING SUB-RESOLUTION ALIGNMENT MARKS ON SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES INCLUDING SAME
(FR) PROCÉDÉS DE PRODUCTION DE REPÈRES D'ALIGNEMENT EN INFRA-RÉSOLUTION SUR DES STRUCTURES DE SEMI-CONDUCTEURS ET STRUCTURES DE SEMI-CONDUCTEURS LES COMPRENANT
Abstract: front page image
(EN)A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.
(FR)La présente invention concerne un procédé de fabrication de structures de semi-conducteurs comprenant des repères d'alignement en infra-résolution. Le procédé comprend les étapes consistant à former un matériau diélectrique sur un substrat, puis à former au moins un repère d'alignement en infra-résolution s'étendant partiellement dans le matériau diélectrique. Il est formé au moins une ouverture dans le matériau diélectrique. L'invention concerne également des structures de semi-conducteurs comprenant les repères d'alignement en infra-résolution.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)