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1. (WO2009058248) STRESS TRANSFER BY SEQUENTIALLY PROVIDING A HIGHLY STRESSED ETCH STOP MATERIAL AND AN INTERLAYER DIELECTRIC IN A CONTACT LAYER STACK OF A SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2009/058248    International Application No.:    PCT/US2008/012195
Publication Date: 07.05.2009 International Filing Date: 28.10.2008
IPC:
H01L 21/8234 (2006.01), H01L 21/8238 (2006.01)
Applicants: ADVANCED MICRO DEVICES, INC. [US/US]; One AMD Place Mail Stop 68 P.O. Box 3453 Sunnyvale, CA 94088-3453 (US) (For All Designated States Except US).
HOHAGE, Joerg [DE/DE]; (DE) (For US Only).
FINKEN, Michael [DE/DE]; (DE) (For US Only).
RICHTER, Ralf [DE/DE]; (DE) (For US Only)
Inventors: HOHAGE, Joerg; (DE).
FINKEN, Michael; (DE).
RICHTER, Ralf; (DE)
Agent: DRAKE, Paul, S.; Advanced Micro Devices, Inc., 7171 Southwest Parkway, Mail Stop B100.3.341, Austin, TX 78735 (US)
Priority Data:
10 2007 052 051.6 31.10.2007 DE
12/108,622 24.04.2008 US
Title (EN) STRESS TRANSFER BY SEQUENTIALLY PROVIDING A HIGHLY STRESSED ETCH STOP MATERIAL AND AN INTERLAYER DIELECTRIC IN A CONTACT LAYER STACK OF A SEMICONDUCTOR DEVICE
(FR) TRANSFERT DE CONTRAINTES PAR LA FOURNITURE SÉQUENTIELLE D'UN MATÉRIAU D'ARRÊT DE GRAVURE CHIMIQUE FORTEMENT CONTRAINT ET D'UN DIÉLECTRIQUE INTERCOUCHES DANS UN EMPILEMENT DE COUCHES DE CONTACT D'UN DISPOSITIF SEMI-CONDUCTEUR
Abstract: front page image
(EN)By forming two or more individual dielectric layers (230, 33OA, 233, 333, 234, 334) of high intrinsic stress levels with intermediate interlayer dielectric material (250A, 350A, 250B, 350B), the limitations of respective deposition techniques, such as plasma enhanced chemical vapor deposition, may be respected while nevertheless providing an increased amount of stressed material above a transistor element (220, 320A), even for highly scaled semiconductor devices (200, 300).
(FR)Par la formation de deux couches diélectriques individuelles ou plus (230, 33OA, 233, 333, 234, 334) présentant des niveaux élevés de contraintes intrinsèques avec un matériau diélectrique intercouches intermédiaire (250A, 350A, 250B, 350B), les limitations de techniques de dépôt respectives, telles que le dépôt chimique en phase vapeur activé par plasma, peuvent être respectées tout en fournissant néanmoins une quantité accrue de matériau contraint au-dessus d'un élément de transistor (220, 320A), même pour des dispositifs semi-conducteurs à grande échelle (200, 300).
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)