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1. (WO2009057385) POWER AMPLIFIER AND POWER AMPLIFIER CONTROL METHOD
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2009/057385    International Application No.:    PCT/JP2008/066095
Publication Date: 07.05.2009 International Filing Date: 05.09.2008
IPC:
H03F 3/24 (2006.01), H01L 21/8234 (2006.01), H01L 27/088 (2006.01), H03F 3/60 (2006.01)
Applicants: NEC CORPORATION [JP/JP]; 7-1, Shiba 5-chome, Minato-ku, Tokyo 1088001 (JP) (For All Designated States Except US).
MARUHASHI, Kenichi [JP/JP]; (JP) (For US Only).
TANOMURA, Masahiro [JP/JP]; (JP) (For US Only).
SHIMAWAKI, Hidenori [JP/JP]; (JP) (For US Only)
Inventors: MARUHASHI, Kenichi; (JP).
TANOMURA, Masahiro; (JP).
SHIMAWAKI, Hidenori; (JP)
Agent: MIYAZAKI, Teruo; 8th Floor, 16th Kowa Bldg. 9-20, Akasaka 1-chome Minato-ku, Tokyo 1070052 (JP)
Priority Data:
2007-283539 31.10.2007 JP
2008-131772 20.05.2008 JP
Title (EN) POWER AMPLIFIER AND POWER AMPLIFIER CONTROL METHOD
(FR) AMPLIFICATEUR DE PUISSANCE ET PROCÉDÉ DE COMMANDE D'AMPLIFICATEUR DE PUISSANCE
(JA) 電力増幅器、電力増幅器の制御方法
Abstract: front page image
(EN)A power amplifier includes a MOS transistor (1) having a gate length of 180 nm or below and an output side matching circuit (5) which is connected to the drain terminal of the MOS transistor (1). Moreover, the MOS transistor (1) has a voltage Vd_n of 0.5 to 0.9 which is normalized by a voltage value allowed in the DC state and the Vd_n is applied as a drain-source voltage. Moreover, the load impedance when the output matching circuit (5) is viewed from the drain terminal is normalized by the gate width W (mm) of the MOS transistor (1) into ZL (= RL + j ·XL), wherein the real part (RL) of the ZL is RL > 0.64 x Vd_n + 0.19 (Ω·mm) and RL < 0.64 x Vd_n + 1.73 (Ω·mm).
(FR)L'invention concerne un amplificateur de puissance comprenant un transistor MOS (12) possédant une longueur de grille de 180 nm ou moins et un circuit d'adaptation côté sortie (5) qui est relié à la borne de train du transistor MOS (1). De plus, le transistor MOS (1) possède une tension Vd_n de 0,5 à 0,9 qui est normalisée par une valeur de tension autorisée dans l'état courant continu, et la tension Vd_n est appliquée en tant que tension drain-source. De plus, l'impédance de charge, lorsque le circuit d'adaptation côté sortie (5) est vu depuis la borne de drain, est normalisée par la largeur de grille W (mm) du transistor MOS (1) en ZL (= RL + j·XL), où la partie réelle (RL) de ZL est RL > 0,64 x Vd_n + 0,19 (Ω·mm) et RL < 0,64 x Vd_n + 1,73 (Ω·mm).
(JA) 本発明の電力増幅器は、ゲート長が180nm以下であるMOSトランジスタ(1)と、MOSトランジスタ(1)のドレイン端子に接続された出力側整合回路(5)と、を有する。また、MOSトランジスタ(1)は、DC状態で許容できる電圧値で規格化された電圧Vd_nが0.5~0.9であり、このVd_nがドレイン-ソース間電圧として印加される。また、ドレイン端子から出力整合回路(5)をみた負荷インピーダンスをMOSトランジスタ(1)のゲート幅W(mm)で規格化した値がZL(=RL+j・XL)であり、ZLの実部(RL)は、RL>0.64×Vd_n+0.19(Ω・mm)で、かつ、RL<0.64×Vd_n+1.73(Ω・mm)である。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)