WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2009057015) TRENCH GATE MOSFET AND METHOD OF MANUFACTURING THE SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2009/057015    International Application No.:    PCT/IB2008/054355
Publication Date: 07.05.2009 International Filing Date: 22.10.2008
IPC:
H01L 29/78 (2006.01), H01L 29/10 (2006.01), H01L 29/40 (2006.01), H01L 21/336 (2006.01), H01L 29/423 (2006.01), H01L 21/265 (2006.01), H01L 21/225 (2006.01)
Applicants: NXP B.V. [NL/NL]; High Tech Campus 60, NL-5656 AG Eindhoven (NL) (For All Designated States Except US).
PEAKE, Steven, Thomas [GB/GB]; (GB) (For US Only).
RUTTER, Philip [GB/GB]; (GB) (For US Only).
ROGERS, Christopher [GB/GB]; (GB) (For US Only).
DROBNIS, Miron [GB/GB]; (GB) (For US Only).
BUTLER, Andrew [GB/GB]; (GB) (For US Only)
Inventors: PEAKE, Steven, Thomas; (GB).
RUTTER, Philip; (GB).
ROGERS, Christopher; (GB).
DROBNIS, Miron; (GB).
BUTLER, Andrew; (GB)
Agent: WHITE, Andrew, G.; c/o NXP Semiconductors, IP Department, Betchworth House, 57-65 Station Road, Redhill Surrey RH1 1DL (GB)
Priority Data:
07119506.9 29.10.2007 EP
Title (EN) TRENCH GATE MOSFET AND METHOD OF MANUFACTURING THE SAME
(FR) MOSFET À GRILLE EN TRANCHÉE ET PROCÉDÉ POUR SA FABRICATION
Abstract: front page image
(EN)A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accomodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.
(FR)L'invention concerne un transistor MOS à effet de champ et grille en tranchée qui présente une région étroite légèrement dopée qui s'étend depuis une région (3) de réception de canal du même type de conductivité en position immédiatement adjacente à la paroi latérale de la tranchée. La région étroite peut être auto-alignée sur le sommet d'une region d'écran inférieure en polysilicium dans la tranchée ou peut s'étendre sur toute la profondeur de la tranchée. La région étroite élargit avantageusement les tolérances de fabrication, qui sinon requièrent un alignement étroit de la grille supérieure en tranchée en polysilicium sur la jonction corps-drain.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, NO, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)